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PDF XC3020 Data sheet ( Hoja de datos )

Número de pieza XC3020
Descripción Field Programmable Gate Arrays
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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No Preview Available ! XC3020 Hoja de datos, Descripción, Manual

Product Obsolete or Under Obsolescence
R
November 9, 1998 (Version 3.1)
0
XC3000 Series
Field Programmable Gate Arrays
(XC3000A/L, XC3100A/L)
0 7* Product Description
Features
• Complete line of four related Field Programmable Gate
Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
• Ideal for a wide range of custom VLSI design tasks
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single
package
- Avoids the NRE, time delay, and risk of conventional
masked gate arrays
• High-performance CMOS static memory technology
- Guaranteed toggle rates of 70 to 370 MHz, logic
delays from 7 to 1.5 ns
- System clock speeds over 85 MHz
- Low quiescent and active power consumption
• Flexible FPGA architecture
- Compatible arrays ranging from 1,000 to 7,500 gate
complexity
- Extensive register, combinatorial, and I/O
capabilities
- High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
- TTL or CMOS input thresholds
- On-chip crystal oscillator amplifier
• Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
• Extensive packaging options
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-grid-
array packages
- Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
• Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
- Excellent reliability record
• Complete Development System
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
Additional XC3100A Features
• Ultra-high-speed FPGA family with six members
- 50-85 MHz system clock rates
- 190 to 370 MHz guaranteed flip-flop toggle rates
- 1.55 to 4.1 ns logic delays
• High-end additional family member in the 22 X 22 CLB
array-size XC3195A device
• 8 mA output sink current and 8 mA source current
• Maximum power-down and quiescent current is 5 mA
• 100% architecture and pin-out compatible with other
XC3000 families
• Software and bitstream compatible with the XC3000,
XC3000A, and XC3000L families
XC3100A combines the features of the XC3000A and
XC3100 families:
• Additional interconnect resources for TBUFs and CE
inputs
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during
initial power-up
• More advanced CMOS process
Low-Voltage Versions Available
• Low-voltage devices function at 3.0 - 3.6 V
• XC3000L - Low-voltage versions of XC3000A devices
• XC3100L - Low-voltage versions of XC3100A devices
Device
XC3020A, 3020L, 3120A
XC3030A, 3030L, 3130A
XC3042A, 3042L, 3142A, 3142L
XC3064A, 3064L, 3164A
XC3090A, 3090L, 3190A, 3190L
XC3195A
Max Logic
Gates
1,500
2,000
3,000
4,500
6,000
7,500
Typical Gate
Range
1,000 - 1,500
1,500 - 2,000
2,000 - 3,000
3,500 - 4,500
5,000 - 6,000
6,500 - 7,500
CLBs
64
100
144
224
320
484
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
22 x 22
User I/Os
Max
64
80
96
120
144
176
Flip-Flops
256
360
480
688
928
1,320
Horizontal
Longlines
16
20
24
32
40
44
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
94,984
7
November 9, 1998 (Version 3.1)
7-3

1 page




XC3020 pdf
Product Obsolete or Under Obsolescence
R
XC3000 Series Field Programmable Gate Arrays
Read or
Write
Q
Configuration
Control
Q
Data
X5382
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
The memory cell outputs Q and Q use ground and VCC lev-
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the development
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in Figure 4, provides an
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
PROGRAM-CONTROLLED MEMORY CELLS
Vcc
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
7
3- STATE
(OUTPUT ENABLE)
OUT
T
O
DIRECT IN
REGISTERED IN
I
Q
DQ
FLIP
FLOP
R
QD
FLIP
FLOP
or
LATCH
R
OK IK
OUTPUT
BUFFER
I/O PAD
TTL or
CMOS
INPUT
THRESHOLD
(GLOBAL RESET)
CK1
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
= PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
November 9, 1998 (Version 3.1)
7-7

5 Page





XC3020 arduino
Product Obsolete or Under Obsolescence
R
XC3000 Series Field Programmable Gate Arrays
Figure 10: FPGA General-Purpose Interconnect.
Composed of a grid of metal segments that may be inter-
connected through switch matrices to form networks for
CLB and IOB inputs and outputs.
Figure 12: CLB X and Y Outputs.
The X and Y outputs of each CLB have single contact,
direct access to inputs of adjacent CLBs
7
Figure 11: Switch Matrix Interconnection Options for
Each Pin.
Switch matrices on the edges are different.
November 9, 1998 (Version 3.1)
7-13

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