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Descripción Field-Programmable Gate Arrays
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R Virtex-II 1.5V
Field-Programmable Gate Arrays
DS031-1 (v1.7) October 2, 2001
00
Summary of Virtex®-II Features
• Industry First Platform FPGA Solution
• IP-Immersion™ Architecture
- Densities from 40K to 8M system gates
- 420 MHz internal clock speed (Advance Data)
- 840+ Mb/s I/O (Advance Data)
• SelectRAM™ Memory Hierarchy
- 3 Mb of True Dual-Port™ RAM in 18-Kbit block
SelectRAM resources
- Up to 1.5 Mb of distributed SelectRAM resources
- High-performance interfaces to external memory
· DDR-SDRAM interface
· FCRAM interface
· QDR-SRAM interface
· Sigma RAM interface
Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
Flexible Logic Resources
- Up to 93,184 internal registers / latches with Clock
Enable
- Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and Sum-of-Products
support
- Internal 3-state bussing
High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
· Precise clock de-skew
· Flexible frequency synthesis
· High-resolution phase shifting
- 16 global clock multiplexer buffers
Active InterconnectTechnology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of
fanout
SelectI/O-UltraTechnology
- Up to 1,108 user I/Os
- 19 single-ended standards and six differential
standards
- Programmable sink current (2 mA to 24 mA) per I/O
Advance Product Specification
- Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
- Differential Signaling
· 840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
· Bus LVDS I/O
· Lightning Data Transport (LDT) I/O with current
driver buffers
· Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
· Built-in DDR Input and Output registers
- Proprietary high-performance SelectLink
Technology
· High-bandwidth data path
· Double Data Rate (DDR) link
· Web-based HDL generation methodology
Supported by Xilinx Foundationand Alliance
Series Development Systems
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Internet Team Design (ITD) tool
SRAM-Based In-System Configuration
- Fast SelectMAPconfiguration
- Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
- IEEE1532 support
- Partial reconfiguration
- Unlimited re-programmability
- Readback capability
0.15 µm 8-Layer Metal process with 0.12 µm
high-speed transistors
1.5 V (VCCINT) core power supply, dedicated 3.3 V
VCCAUX auxiliary and VCCO I/O power supplies
IEEE 1149.1 compatible boundary-scan logic support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
packages in three standard fine pitches (0.80mm,
1.00mm, and 1.27mm)
100% factory tested
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-1 (v1.7) October 2, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1

1 page




XC2V1000-6FG456I pdf
R Virtex-II 1.5V Field-Programmable Gate Arrays
Boundary Scan
Boundary scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II devices that complies with IEEE standards
1149.1 - 1993 and 1532. A system mode and a test mode
are implemented. In system mode, a Virtex-II device per-
forms its intended mission even while executing non-test
boundary-scan instructions. In test mode, boundary-scan
test instructions control the I/O pins for testing purposes.
The Virtex-II Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Configuration
Virtex-II devices are configured by loading data into internal
configuration memory, using the following five modes:
Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE 1532)
A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration
information.
Readback and Integrated Logic Analyzer
Configuration data stored in Virtex-II configuration memory
can be read back for verification. Along with the configura-
tion data, the contents of all flip-flops/latches, distributed
SelectRAM, and block SelectRAM memory resources can
be read back. This capability is useful for real-time debug-
ging.
The Integrated Logic Analyzer (ILA) core and software pro-
vides a complete solution for accessing and verifying
Virtex-II devices.
Virtex-II Device/Package Combinations
and Maximum I/O
Wire-bond and flip-chip packages are available. Table 4 and
Table 5 show the maximum possible number of user I/Os in
wire-bond and flip-chip packages, respectively. Table 6
shows the number of available user I/Os for all device/pack-
age combinations.
CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
BG denotes standard BGA (1.27 mm pitch).
BF denotes flip-chip BGA (1.27 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD) and VBATT.
Table 4: Wire-Bond Packages Information
Package
CS144
FG256
Pitch (mm)
0.80 1.00
Size (mm)
12 x 12
17 x 17
I/Os 92 172
FG456
1.00
23 x 23
324
FG676
1.00
27 x 27
484
BG575
1.27
31 x 31
408
BG728
1.27
35 x 35
516
Table 5: Flip-Chip Packages Information
Package
FF896
Pitch (mm)
1.00
Size (mm)
31 x 31
I/Os 624
FF1152
1.00
35 x 35
824
FF1517
1.00
40 x 40
1,108
BF957
1.27
40 x 40
684
DS031-1 (v1.7) October 2, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
5

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