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PDF XC17256EVO8I Data sheet ( Hoja de datos )

Número de pieza XC17256EVO8I
Descripción Configuration PROMs
Fabricantes Xilinx 
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0
R XC1700E and XC1700L Series
Configuration PROMs
DS027 (v3.1) July 5, 2000
08
Features
• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• XC17128E/EL, XC17256E/EL, XC1701 and XC1700L
series support fast configuration
• Low-power CMOS Floating Gate process
• XC1700E series are available in 5V and 3.3V versions
• XC1700L series are available in 3.3V only
• Available in compact plastic packages: 8-pin SOIC,
8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Guaranteed 20 year life data retention
Product Specification
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
VCC VPP GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1

1 page




XC17256EVO8I pdf
R
VCC
XC1700E and XC1700L Series Configuration PROMs
DOUT
FPGA
MODES*
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
VCC
RESET
RESET
DIN
CCLK
DONE
INIT
3.3V
4.7K
VCC VPP
DATA
CLK PROM
CE CEO
OE/RESET
* For mode pin connections,
refer to the appropriate FPGA data sheet.
(Low Resets the Address Pointer)
CCLK
(Output)
DATA
CLK
CE
Cascaded
Serial
Memory
OE/RESET
DIN
DOUT
(Output)
DS027_02_060100
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
5

5 Page





XC17256EVO8I arduino
R XC1700E and XC1700L Series Configuration PROMs
Ordering Information
XC1701L PC20 C
Device Number
XC1736E
XC1765E
XC1765EL
XC17128E
XC17128EL
XC17256E
XC17256EL
XC17512L
XC1701
XC1701L
XC1704L
XC1702L
Package Type
PD8 = 8-pin Plastic DIP
SO8 = 8-pin Plastic Small-Outline Package
VO8 = 8-pin Plastic Small-Outline Thin Package
SO20 = 20-pin Plastic Small-Outline Package
PC20 = 20-pin Plastic Leaded Chip Carrier
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
Operating Range/Processing
C = Commercial (TA = 0° to +70°C)
I = Industrial (TA = 40° to +85°C)
Valid Ordering Combinations
XC1736EPD8C XC1765EPD8C XC17128EPD8C XC17256EPD8C XC1701PD8C XC1702LVQ44C
XC1736ESO8C XC1765ESO8C XC17128EVO8C XC17256EVO8C XC1701PC20C XC1702LPC44C
XC1736EVO8C XC1765EVO8C XC17128EPC20C XC17256EPC20C XC1701SO20C XC1704LVQ44C
XC1736EPC20C XC1765EPC20C XC17128EPD8I
XC17256EPD8I
XC1701PD8I XC1704LPC44C
XC1736EPD8I XC1765EPD8I XC17128EVO8I XC17256EVO8I XC1701PC20I XC1702LVQ44I
XC1736ESO8I XC1765ESO8I XC17128EPC20I XC17256EPC20I XC1701SO20I XC1702LPC44I
XC1736EVO8I XC1765EVO8I
XC1704LVQ44I
XC1736EPC20I XC1765EPC20I
XC1704LPC44I
XC1765ELPD8C XC17128ELPD8C XC17256ELPD8C XC1701LPD8C XC17512LPD8C
XC1765ELSO8C XC17128ELVO8C XC17256ELVO8C XC1701LPC20C XC17512LPC20C
XC1765ELVO8C XC17128ELPC20C XC17256ELPC20C XC1701LSO20C XC17512LSO20C
XC1765ELPC20C XC17128ELPD8I XC17256ELPD8I XC1701LPD8I XC17512LPD8I
XC1765ELPD8I XC17128ELVO8I XC17256ELVO8I XC1701LPC20I XC17512LPC20I
XC1765ELSO8I XC17128ELPC20I XC17256ELPC20I XC1701LSO20I XC17512LSO20I
XC1765ELVO8I
XC1765ELPC20I
DS027 (v3.1) July 5, 2000
Product Specification
www.xilinx.com
1-800-255-7778
11

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