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PDF X98027 Data sheet ( Hoja de datos )
| Número de pieza | X98027 | |
| Descripción | PRELIMINARY INFORMATION | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Key Features
– Resolutions Up To QXGA 60Hz
– 250ps Long Term Jitter
– 64 Phase Choices
– Zero Offset Error/Offset Drift
X98027
275MHz Triple Video Digitizer
with Digital PLL
PRELIMINARY INFORMATION
FEATURES
• 275MSPS maximum conversion rate
• 64 interpixel sampling positions
• Low long-term PLL clock jitter (250ps p-p @ 275MSPS)
• Programmable input bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
• RGB and YUV 4:2:2 output formats
• 4 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
• Trilevel Sync detection
• 1180mW typical PD @ 275MSPS
APPLICATIONS
• LCD Monitors and Projectors
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
• Scan Converters
DESCRIPTION
The X98027 3-channel, 8-bit Analog Front End (AFE) contains
all the components necessary to digitize analog RGB or YUV
graphics signals from personal computers, workstations and
video set-top boxes. The fully differential analog design provides
high PSRR and dynamic performance to meet the strigent
requirements of the graphics display industry. The 275MSPS
conversion rate supports resolutions up to QXGA at 60Hz
refresh rate, while the front end's high input bandwidth ensures
sharp images at the highest resolution.
To minimize noise, the X98027's analog section features 2 sets
of pseudo-differential RGB inputs with programmable input
bandwidth, as well as internal DC restore clamping (including
mid-scale clamping for YUV signals). This is followed by the
programmable gain/offset stage and the three 275MSPS
Analog-to-Digital Converters (ADCs). All necessary reference
voltages are internally generated.
The X98027's digital PLL generates a pixel clock from the analog
source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock
output frequencies range from 10MHz to 275MHz with long-term
clock jitter less than 250ps peak to peak.
BLOCK DIAGRAM
VCLAMP
Offset
DAC
10
Auto Black
Level
Compensation
RIN1
VIN+
RIN2 VIN- PGA + 8 bit ADC
8
8 RP[7:0]
8 RS[7:0]
GIN1
RGBGND1
GIN2
RGBGND2
BIN1
BIN2
VCLAMP
VIN+
VIN- PGA
VCLAMP
VIN+
VIN- PGA
Offset
DAC
10
Auto Black
Level
Compensation
+ 8 bit ADC
8
Offset
DAC
10
Auto Black
Level
Compensation
+ 8 bit ADC
8
8 GP[7:0]
8 GS[7:0]
8 BP[7:0]
8 BS[7:0]
SOGIN1
SOGIN2
HSYNCIN1
HSYNCIN2
VSYNCIN1
VSYNCIN2
CLOCKINV
XTALIN
XTALOUT
SCL
SDA
SADDR
Sync
Processing
Digital PLL
Serial
Interface
AFE Configuration
and Control
DATACLK
DATACLK
HSOUT
VSOUT
HSYNCOUT
VSYNCOUT
XTALCLKOUT
REV 0.7 9/21/03
www.xicor.com
Characteristics subject to change without notice
1 page | ||
| Páginas | Total 1 Páginas | |
| PDF Descargar | [ Datasheet X98027.PDF ] | |
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