PDF X9470 Data sheet ( Hoja de datos )

Número de pieza	X9470
Descripción	RF Power Amplifier (PA) Bias Controller
Fabricantes	Xicor
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Preliminary Information RF Power Ampliﬁer (PA) Bias Controller X9470 FEATURES • Programmable Bias Controller IC for Class A and AB LDMOS Power Ampliﬁers • Adaptive System on Chip Solution • Bias Current Calibration to better than ±4% using Reference Trim DCP • Automatic Bias Point Tracking and Calibration — IDQ Sensing and Tracking —Programmable Instrumentation Ampliﬁer to Scale Wide Range of IDQ —Programmable Gate Bias Driver —All Programmable settings are Nonvolatile —All Settings Recalled at Power Up. • 28V Maximum VDD • 2 Wire Interface for Programming Bias Setting and Optimizing IDQ Set Point • Bias Level Comparator • Shutdown Control pin for PA Signal • Slave address to allow for multiple devices • 24-pin TSSOP Package • Applications: Cellular Base Stations (GSM, UMTS, CDMA, EDGE), TDD applications, Point- to-multipoint, and other RF power transmission systems DESCRIPTION The Xicor X9470 RF PA Bias Controller contains all of the necessary analog components to sense the PA drain current through an external sense resistor and automatically control the gate bias voltage of an LDMOS PA. The external sense resistor voltage is ampliﬁed by an instrumentation ampliﬁer and the out- put of the ampliﬁer along with an external reference voltage is fed to the inputs of a comparator. The com- parator output indicates which direction the LDMOS gate bias voltage will move in the next calibration cycle. System calibration is accomplished by enabling the X9470 and providing a clock to the SCL pin. The LDMOS drain current can be maintained constant over temperature and aging changes by periodic calibra- tion. The VOUT pin can be used to monitor the aver- age power by tracking the drain current. Up to eight X9470 or additional Xicor Digital Potentiometers can be controlled via a two-wire serial bus. TYPICAL APPLICATION INC/DEC RWREF RHREF RLREF AGND VOUT V+ VDD A2 RREF A1 VREF Comparator A0 VP Instrumentation Amplifier VSENSE+ CBULK ∆V VSENSE– RSENSE SDA SCL I2C interface Control & Status Registers EEPROM VCC VSS Vbias control VREF control RBIAS + – CS RHBIAS RWBIAS RLBIAS SHDN choke VBIAS FILTER RF PA in Matching RF Impedance Class A Example RF out REV 11.16 3/20/03 www.xicor.com 1 of 25 1 page Preliminary Information X9470 VREF DCP CIRCUIT BLOCK Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless otherwise noted.) Symbol Parameter Resolution(10) Absolute Linearity(6) Relative Linearity(7) RTOTAL Temperature Coefficient(10) Ratiometric Temperature Coefficient(10) CIN(10) Potentiometer Capacitances on RHREF and RLREF Min. -0.2 -0.2 -20 Limits Typ. Max. 1.6 +0.2 +0.2 ±300 +20 10 Units % MI(8) MI(8) ppm/°C ppm/°C pF Test Conditions/Notes BIAS ADJUSTMENT DCP CIRCUIT BLOCK Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V;Vsense+, Vsense- = 26V;TA = -40°C to +85°C, unless otherwise noted.) Symbol Parameter RTOTAL End to End Resistance Variation Number Taps or Positions VRH VRL VRW Voltage at the RHBIAS Terminal Voltage Voltage at the RLBIAS Terminal Voltage Voltage at the RWBIAS Terminal Voltage Power Rating(10) Resolution(10) Absolute Linearity(6) Relative Linearity(7) RTOTAL Temperature Coefficient(10) Ratiometric Temperature Coefficient(10) CIN(10) Potentiometer Capacitances on RHBIAS and RLBIAS Min. 8 AGND AGND AGND -1.0 -1.0 -50 Limits Typ. Max. 10 12 256 V+ V+ V+ 2.5 0.4 +1.0 +1.0 ±300 50 10 Units Test Conditions/Notes KΩ with ±20% variation V AGND = 0V V AGND = 0V V AGND = 0V mW RTOTAL =10 KΩ % MI(8) MI(8) ppm/°C ppm/°C pF VBIAS OUTPUT VOLTAGE FOLLOWER Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40°C to +85°C, unless otherwise noted.) Symbol Parameter VOS Input Offset Voltage VOSDRIFT(10) Offset Voltage Temperature Coefficient SR Output Slew Rate on VBIAS VBIAS Voltage Output Swing Min. Limits Typ. Max. 10 10 Units mV µV/°C Test Conditions/Notes TA = -40 to +85°C 0.5 V/µS RL = 10kΩ, 1nF, ∆VBIAS = 20mV 1.5 VCC – 0.5 V IOUT = ±10mA REV 11.16 3/20/03 www.xicor.com 5 of 25 5 Page Preliminary Information X9470 VOUT This pin is the output of the IA, which reﬂects a 20x or 50x gain of the input signal (voltage across the Vsense pins). It can be used to indicate the magnitude of the drain current envelope when RF is present. Output Block Pins VBIAS The VBIAS is the gate bias voltage output. It is buffered with a unity gain ampliﬁer and is capable of driving 1nF (typical) capacitive loads. This pin is intended to be connected through an RF ﬁl- ter to the gate of an LDMOS power transistor. The volt- age of VBIAS is determined by the XDCP’s value of the RBIAS resistor. Other Pins SHDN SHDN is an input pin that is used to shutdown the VBIAS output voltage follower. When the SHDN pin is HIGH, the VBIAS pin is pulled to VSS. When the device is shutdown, the current RBIAS wiper position will be maintained in the wiper counter register. When shut- down is disabled, the wiper returns to the same wiper position before shutdown was invoked. Note that when the device is taken out of shutdown mode (SHDN goes from HIGH to LOW), the CS input must be cycled once to enable calibration. SDA Serial bus data input/output. Bi-directional. External pullup is required. A0, A1, A2 Serial bus slave address pins. These pins are used to deﬁned a hardware slave address. This will allow up to 8 of the X9470’s to be shared on one two-wire bus. These are useful if several X9470’s are used to control the bias voltages of several LDMOS Power Transistors in a single application. Default hardware slave address is “000” if left unconnected due to internal pull-down resistor. TYPICAL APPLICATION The X9470 can be used along with a microprocessor and transmit control chips to control and coordinate FET biasing (see Figure 1). The CS, SCL, and SDA signals are required to control the X9470 Bias Adjust- ment Circuit Block. An internal RWREF voltage is pro- vided via a programmable voltage divider between the RHREF and RLREF pins and is used to set the voltage reference of the comparator. The shutdown (SHDN) and bias voltage indicators (INC/DEC) are additional functions that offer FET control, monitoring, and pro- tection. Typically, the closed loop setup of the X9470 allows for ﬁnal calibration of a power ampliﬁer at production test. The CS and SCL pins are used to perform this calibra- tion function. Once in a base station, the ampliﬁer can then be re-calibrated any time that there is no RF sig- nal present. The bias setting block can also be used open loop to adjust gate bias or can be shutdown using the SHDN pin. The sense and scale block can be used for ampliﬁer power monitoring diagnostics as well. The range of the drain bias current operating point of the LDMOS FET is set by an external reference across the reference potentiometer. The wiper of the potenti- ometer sets the trip point for comparison with VP, the ampliﬁed voltage across RSENSE, the drain resistor. The output of the comparator causes the RBIAS poten- tiometer to increment or decrement automatically on the next SCL clock cycle. This RBIAS potentiometer is conﬁgured as a voltage divider with a buffered wiper output which drives the gate voltage of an external LDMOS FET. Once the optimum bias point is reached, the RBIAS value is latched into a wiper counter register. Again, the VBIAS gate voltage can be updated continuously or periodically depending on the system requirements. Both terminals of the RBIAS potentiometer are access- ible and can be driven by external reference voltages to achieve a desired IDQ vs. gate voltage resolution, as well as supporting temperature compensation circuitry. In summary, the X9470 provides full ﬂexibility on set- ting the operating bias point and range of an external RF power ampliﬁer for GSM, EDGE, UMTS, CDMA or other similar applications. REV 11.16 3/20/03 www.xicor.com 11 of 25 11 Page

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