DataSheet.es    


PDF ZL50234 Data sheet ( Hoja de datos )

Número de pieza ZL50234
Descripción 8 Channel Voice Echo Canceller
Fabricantes ETC 
Logotipo ETC Logotipo



Hay una vista previa y un enlace de descarga de ZL50234 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! ZL50234 Hoja de datos, Descripción, Manual

ZL50234
8 Channel Voice Echo Canceller
Data Sheet
Features
• Independent multiple channels of echo
cancellation; from 8 channels of 64ms to 4
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
• Independent Power Down mode for each group of
2 channels for power management
• Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
• Passed AT&T voice quality testing for carrier
grade echo cancellers.
• Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
• PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
• Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
• Per channel echo canceller parameters control
• Transparent data transfer and mute
• Fast reconvergence on echo path changes
• Fully programmable convergence speeds
• Patented Advanced Non-Linear Processor with
high quality subjective performance
• Protection against narrow band signal divergence
and instability in high echo environments
March 2003
Ordering Information
ZL50234/QCC 100-Pin LQFP
ZL50234/GDC 208-Ball LBGA
-40°C to +85°C
• 0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
• Offset nulling of all PCM channels
• 10 MHz or 20 MHz master clock operation
• 3.3 V I/O pads and 1.8V Logic core operation with
5-Volt tolerant inputs
• IEEE-1149.1 (JTAG) Test Access Port
• ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Applications
• Voice over IP network gateways
• Voice over ATM, Frame Relay
• T1/E1/J1 multichannel echo cancellation
• Wireless base stations
• Echo Canceller pools
• DCME, satellite and multiplexer system
VDD1 (3.3V)
VSS
VDD2 (1.8V)
ODE
Rin
Sin
MCFLseKl
C4i
F0i
Serial
to
Parallel
PLL
Timing
Unit
Echo Canceller Pool
Parallel
to
Serial
Group 0
ECA/ECB
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Microprocessor Interface
Test Port
Rout
Sout
RESET
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50234 Device Overview
1

1 page




ZL50234 pdf
Data Sheet
ZL50234
Pin Description (continued)
PIN
Name
PIN #
208-Ball LBGA
100 PIN
LQFP
Description
DS R11
10 Data Strobe (Input). This active low input works in conjunction
with CS to enable the read and write operations.
CS R13
11 Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
R/W R5
12 Read/Write (Input). This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
DTA
R7
13 Data Transfer Acknowledgment (Open Drain Output). This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1K typical) is required at this output.
D0..D7
T2,T4,T6,T8,T9,T11,
T13,T15
15, 16, 17, Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit
19, 20, 21, bidirectional data bus of the microprocessor port.
22, 23
A0..A10
P16,N16,M16,L16,K16,
J16,H16,G16,F16,E16,
D16
28, 29, 30, Address A0 to A10 (Input). These inputs provide the A10 - A0
31, 33, 34, address lines to the internal registers.
35, 36, 38,
39, 40
ODE
B13
57 Output Drive Enable (Input). This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Sout
A8
58 Send PCM Signal Output (Output). Port 1 TDM data output
streams. Sout pin outputs serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
Rout
B9
59 Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
Sin B11
60 Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s with 8
channels per stream.
Rin B7
61 Receive PCM Signal Input (Input). Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
F0i B5
62 Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
C4i A4
63 Serial Clock (Input). 4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
MCLK
G2
90 Master Clock (Input). Nominal 10MHz or 20MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Zarlink Semiconductor Inc.
5

5 Page





ZL50234 arduino
Data Sheet
ZL50234
1.6 Instability Detector
In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability
problems in the adaptive filter. This instability can result in variable pitched ringing or oscillation. Should this ringing
occur, the Instability Detector will activate and suppress the oscillations.
The Instability Detector is activated by setting the RingClr bit in Control Register 3 to “1”.
1.7 Narrow Band Signal Detector (NBSD)
Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a
prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is
designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow
band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.
The NBSD will be active regardless of the Echo Canceller functional state. However the NBSD can be disabled by
setting the NBDis bit to “1” in Control Register 2.
1.8 Offset Null Filter
Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC
component, the ZL50234 incorporates Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.
1.9 Adjustable Level Pads
The ZL50234 provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be
adjusted both inside and outside the echo path. Each signal level may be independently scaled with anywhere from
0 to -12 dB level, in 3 dB steps. Level values are set using the Gains register.
CAUTION: Gain adjustment can help interface the ZL50234 to a particular system in order to provide optimum echo
cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels
and slow convergence. Exercise great care when adjusting these values.
The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of
attenuation at Rin, and override the values in the Gains register.
1.10 ITU-T G.168 Compliance
The ZL50234 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes
(i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.
The ZL50234 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50234
was classified as “carrier grade” echo canceller.
2.0 Device Configuration
The ZL50234 architecture contains 8 echo cancellers divided into 4 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in three
distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.
Zarlink Semiconductor Inc.
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet ZL50234.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ZL502334 Channel Voice Echo CancellorETC
ETC
ZL50233GD4 Channel Voice Echo CancellorETC
ETC
ZL50233GDC4 Channel Voice Echo CancellorETC
ETC
ZL50233QC4 Channel Voice Echo CancellorETC
ETC

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar