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PDF ZL38001 Data sheet ( Hoja de datos )

Número de pieza ZL38001
Descripción Low-Voltage Acoustic Echo Canceller with Low ERL Compensation
Fabricantes Zarlink Semiconductor Inc 
Logotipo Zarlink Semiconductor Inc Logotipo



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ZL38001
Low-Voltage Acoustic Echo Canceller
with Low ERL Compensation
Data Sheet
Features
• Contains two echo cancellers: 112 ms acoustic
echo canceller
• Works with low cost voice codec. ITU-T G.711 or
signed mag µ/A-Law, or linear 2’s comp
• Each port may operate in different format
• Advanced NLP design - full duplex speech with
no switched loss on audio paths
• Fast re-convergence time: tracks changing echo
environment quickly
• Adaptation algorithm converges even during
Double-Talk
• Designed for exceptional performance in high
background noise environments
• Provides protection against narrow-band signal
divergence
• Howling prevention stops uncontrolled oscillation
in high loop gain conditions
• Offset nulling of all PCM channels
• Serial micro-controller interface
June 2004
Ordering Information
ZL38001DGA 36 Pin QSOP
ZL38001QDC 48 Pin TQFP
-40°C to +85°C
• ST-BUS, GCI, or variable-rate SSI PCM interfaces
• User gain control provided for speaker path
(-24 dB to +48 dB in 3 dB steps)
• 18 dB gain at Sout to compensate for high ERL
environments
• AGC on speaker path
• Handles up to 0 dB acoustic echo return loss
• Transparent data transfer and mute options
• 20 MHz master clock operation
• Low power mode during PCM Bypass
• Bootloadable for future factory software upgrades
• 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Sin
MD1
MD2
Rout
µ/A-Law/
Linear
Offset
Null
NBSD
S1 + +
-
Limiter
S2 ADV
S3
NLP
18dB
Gain
Linear/
µ/A-Law
Adaptive
Filter
R3
CONTROL
UNIT
Double
Talk
Detector
Program
RAM
Program
ROM
Micro
Interface
Howling
R1 NBSD Controller
Linear/
µ/A-Law
-24 -> +48dB
AGC
User
Gain
Limiter
R2
Offset
Null
µ/A-Law/
Linear
VDD
VSS
RESET FORMAT ENA2
ENA1 LAW F0i BCLK/C4i MCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
Sout
DATA1
DATA2
SCLK
CS
Rin

1 page




ZL38001 pdf
ZL38001
Data Sheet
Table of Contents
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Adaptation Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Advanced Non-Linear Processor (ADV-NLP)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Howling Detector (HWLD)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 User Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8 AGC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9 18 dB Gain Pad at Sout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.10 Mute Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.11 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.12 Adaptation Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.13 ZL38001 Throughput Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.14 Power Down / Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 PCM Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 ST-BUS and GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 PCM Law and Format Control (LAW, FORMAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Linear PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Bit Clock (BCLK/C4i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Master Clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.0 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Bootload Process and Execution from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.0 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
Zarlink Semiconductor Inc.

5 Page





ZL38001 arduino
ZL38001
Data Sheet
1.8 AGC
The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically
reduced during the following conditions:
• When clipping of the receive signal occurs
• When initial convergence of the acoustic echo canceller detects unusually large echo return
• When howling is detected
• The AGC can be disabled by setting the AGC- bit to 1 in MC control register
1.9 18 dB Gain Pad at Sout
The purpose of the 18 dB gain pad is to improve the subjective quality in low ERL environments. The ZL38001 can
cancel echo with a ERL as low as 0 dB (attenuation from Rout to Sin). In many hand free applications, the ERL can
be low (or negative). This is due to both speaker and microphone gain setting. The speaker gain has to be set high
enough for the speaker to be heard properly and the microphone gain needs to be set high enough to ensure
sufficient signal is sent to the far end. If the ERL (Acoustic Attenuation - speaker gain - microphone gain) is greater
than 0 dB, then the echo canceller cannot cancel echo. To overcome this limitation, the ZL38001 has a 18 dB gain
pad at Sout. The microphone gain can be reduced by 18 dB to allow either the speaker gain and/or the acoustic
coupling to be increased by a total of 18 dB allowing more flexibility in the design.
1.10 Mute Function
A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R
or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively.
Quiet code is defined according to the following table.
+Zero
(quiet code)
LINEAR
16 bits
2’s complement
0000h
SIGN/
MAGNITUDE
µ-Law
A-Law
80h
CCITT (G.711)
µ-Law
A-Law
FFh D5h
Table 1 - Quiet PCM Code Assignment
11
Zarlink Semiconductor Inc.

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