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PDF ZL30402 Data sheet ( Hoja de datos )
| Número de pieza | ZL30402 | |
| Descripción | SONET/SDH Network Element PLL | |
| Fabricantes | Zarlink Semiconductor Inc | |
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ZL30402
SONET/SDH Network Element PLL
Features
• Meets requirements of GR-253 for SONET
stratum 3 and SONET Minimum Clocks (SMC)
• Meets requirements of GR-1244 for stratum 3
• Meets requirements of G.813 Option 1 and 2 for
SDH Equipment Clocks (SEC)
• Generates clocks for ST-BUS, DS1, DS2, DS3,
OC-3, E1, E2, E3, STM-1 and 19.44 MHz
• Holdover accuracy to 1x10 -12 meets GR-1244
Stratum 3E and ITU-T G.812 requirements
• Continuously monitors Primary and Secondary
reference clocks
• Provides “hit-less” reference switching
• Compensates for Master Clock Oscillator
accuracy
• Detects frequency of both reference clocks and
synchronizes to any combination of 8 kHz,
1.544 MHz, 2.048 MHz and 19.44 MHz reference
frequencies.
• Allows Hardware or Microprocessor control
• Pin compatible with MT90401 device.
Applications
• Synchronization for SDH and SONET Network
Elements
• Clock generation for ST-BUS and GCI
backplanes
Data Sheet
November 2004
Ordering Information
ZL30402/QCC 80 Pin LQFP Trays
ZL30402QCC1 80 Pin LQFP* Trays
*Pb Free Matte Tin
-40°C to +85°C
Description
The ZL30402 is a Network Element Phase-Locked
Loop designed to synchronize SDH and SONET
systems. In addition, it generates multiple clocks for
legacy PDH equipment and provides timing for ST-BUS
and GCI backplanes.
The ZL30402 operates in NORMAL (LOCKED),
HOLDOVER and FREE-RUN modes to ensure that in
the presence of jitter, wander and interruptions to the
reference signals, the generated clocks meet
international standards. The filtering characteristics of
the PLL are hardware or software selectable and they
do not require any external adjustable components.
The ZL30402 uses an external 20 MHz Master Clock
Oscillator to provide a stable timing source for the
HOLDOVER operation.
The ZL30402 operates from a single 3.3 V power
supply and offers a 5 V tolerant microprocessor
interface.
VDD GND
C20i
FCS
PRI
SEC
RefSel
HW
RESET
Primary
Acquisition
PLL
Secondary
Acquisition
PLL
Master Clock
Frequency
Calibration
MUX
Microport
Core PLL
APLL
Clock
Synthesizer
Control State Machine
JTAG
IEEE
1149.1a
CS DS R/W A0-A6 D0-D7
MS1 MS2 RefAlign LOCK HOLDOVER
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
C155P/N
C34/C44
C19o
C16o
C8o
C6o
C4o
C2o
C1.5o
F16o
F8o
F0o
E3DS3/OC3
E3/DS3
Tclk
Tdi
Tdo
Tms
Trst
1 page  
ZL30402
Data Sheet
Pin Description (continued)
Pin #
Name
Description
20 F8o Frame Pulse ST-BUS/GCI 8.192 Mb/s (CMOS tristate output). This is an
8 kHz, 122 ns, active high framing pulse, which marks the beginning of a ST-
BUS/GCI frame. This is typically used for ST-BUS/GCI operation at
8.192 Mb/s. See Figure 13 for details.
21 E3DS3/OC3 E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin
enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155
clock outputs (high impedance) and sets C34/C44 output to provide C34 and
C44 clocks. In Software Control connect this pin to ground.
22
E3/DS3
E3 or DS3 Selection (Input). In Hardware Control, when the E3DS3/OC3 pin
is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44
output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set
low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and
logic high selects 8.592 MHz clock. Connect this input to ground in Software
Control.
23
SEC
Secondary Reference (Input). This input is used as a secondary reference
source for synchronization. The ZL30402 can synchronize to the falling edge
of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the
19.44 MHz clock. In Hardware Control, selection of the input reference is
based upon the RefSel control input. This pin is internally pulled up to VDD.
24 PRI Primary Reference (Input). This input is used as a primary reference source
for synchronization. The ZL30402 can synchronize to the falling edge of the
8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz
clock. In Hardware Control, selection of the input reference is based upon the
RefSel control input. This pin is internally pulled up to VDD.
25
GND
Ground.
26 IC Internal Connection. Leave unconnected.
27
GND
Ground.
28
AVDD
Positive Analog Power Supply. Connect this pin to VDD.
29
VDD
Positive Power Supply.
30
C155N
Clock 155.52 MHz (LVDS output). Differential outputs for a 155.52 MHz clock.
31
C155P
These outputs are enabled by applying logic low to E3DS3/OC3 input or they
can be switched into high impedance state by applying logic high.
32
GND
Ground.
33 NC No internal bonding Connection. Leave unconnected.
34 Tdo IEEE1149.1a Test Data Output (CMOS output). JTAG serial data is output on
this pin on the falling edge of Tclk clock. If not used, this pin should be left
unconnected.
5
Zarlink Semiconductor Inc.
5 Page 
ZL30402
Data Sheet
C155 Output
C19o Output
C34/44 Output
E3DS3/OC3
01
155.52 HIZ
E3DS3/OC3
01
19.44 19.44
Dejittered
E3DS3/OC3
01
0 11.184 44.736
1 8.592 34.368
Figure 4 - C19o, C155o, C34/C44 Clock Generation Options
All clocks and frame pulses except the C155 are output with CMOS logic levels. The C155 clock (155.52MHz) is
output in a standard LVDS format.
2.5 Output Clocks Phase Adjustment
The ZL30402 provides three control registers dedicated to programming the output clock phase offset. Clocks
C16o, C8o, C4o and C2o and frame pulses F16o, F8o, F0o are derived from 16.384 MHz and can be jointly shifted
with respect to an active reference clock by up to 125 µs with a step size of 61 ns. The required phase shift of
clocks is programmable by writing to the Phase Offset Register 2 ("Table 8") and to the Phase Offset Register 1
("Table 9"). The C1.5o clock can be shifted as well in step sizes of 81ns by programming C1.5POA bits in Control
Register 3 ("Table 11").
The coarse phase adjustment is augmented with a very fine phase offset control on the order of 477 ps per step.
This fine adjustment is programmable by writing to the Fine Phase Offset Register (Table 15 "Fine Phase Offset
Register (R/W)"). The offset moves all clocks and frame pulses generated by ZL30402 including C155 clock.
2.6 Control State Machine
2.6.1 Clock Modes
Any Network Element that operates in a synchronous network must support three Clock Modes: Free-run, Normal
(Locked) and Holdover. These clock modes determine behavior of a Network Element to the unforeseen changes in
the network synchronization hierarchy. Requirements for Clock Modes are defined in the international standards
e.g.: G.813, GR-1244-CORE and GR-253-CORE and they are very strictly enforced by network operators. The
ZL30402 supports all clock modes and each of these modes have a corresponding state in the Control State
Machine.
2.6.2 ZL30402 State Machine
The ZL30402 Control State Machine is a complex combination of many internal states supporting the three
mandatory clock modes. The simplified version of this state machine is shown in Figure 5 and it includes the
mandatory states: Free-run, Normal and Holdover. These three states are complemented by two additional states:
Reset and Auto Holdover, which are critical to the ZL30402 operation under the changing external conditions.
11
Zarlink Semiconductor Inc.
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| PDF Descargar | [ Datasheet ZL30402.PDF ] | |
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