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PDF Z89C00 Data sheet ( Hoja de datos )

Número de pieza Z89C00
Descripción 16-BIT DIGITAL SIGNAL PROCESSOR
Fabricantes Zilog. 
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ZILOG
PRELIMINARY
Z89C00
16-BIT DIGITAL SIGNAL PROCESSOR
PRELIMINARY PRODUCT SPECIFICATION
FEATURES
s 16-Bit Single Cycle Instructions
s Zero Overhead Hardware Looping
s 16-Bit Data
s Ready Control for Slow Peripherals
s Single Cycle Multiply/Accumulate (100 ns)
s Six-Level Stack
s 512 Words of On-Chip RAM
s Static Single-Cycle Operation
Z89C00
16-BIT DIGITAL
SIGNAL PROCESSOR
s 16-Bit I/O Port
s 4K Words of On-Chip Masked ROM
s Three Vectored Interrupts
s 64K Words of External Program Address Space
s Two Conditional Branch Inputs/Two User Outputs
s 24-Bit ALU, Accumulator and Shifter
s IBM® PC Development Tools
GENERAL DESCRIPTION
The Z89C00 is a second generation, 16-bit, fractional,
two’s complement CMOS Digital Signal Processor (DSP).
Most instructions, including multiply and accumulate,
are accomplished in a single clock cycle. The processor
contains 1 Kbyte of on-chip data RAM (two blocks of
256 16-bit words), 4K words of program ROM and 64K
words of program memory addressing capability. Also,
the processor features a 24-bit ALU, a 16 x 16 multiplier, a
24-bit Accumulator and a shifter. Additionally, the processor
contains a six-level stack, three vectored interrupts and
two inputs for conditional program jumps. Each RAM block
contains a set of three pointers which may be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be
simultaneously addressed and loaded to the multiplier for
a true single cycle multiply.
There is a 16-bit address and a 16-bit data bus for external
program memory and data, and a 16-bit I/O bus for
transferring data. Additionally, there are two general
purpose user inputs and two user outputs. Operation with
slow peripherals is accomplished with a ready input pin.
The clock may be stopped to conserve power.
Development tools for the IBM PC include a relocatable
assembler, a linker loader, and an ANSI-C compiler. Also,
the development tools include a simulator/debugger, a
cross assembler for the TMS320 family assembly code
and a hardware emulator.
To assist the user in understanding the Z89C00 DSP Q15
two's complement fractional multiplication, an application
note has been included in this product specification as an
appendix.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
DC 4083-00
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Z89C00 pdf
ZILOG
PRELIMINARY
Z89C00
16-BIT DIGITAL SIGNAL PROCESSOR
PD15-PD0 Program Memory Data Input (input). Instruc-
tions or data are read from the address specified by PD15-
PD0, through these pins and are executed or stored.
/RES Reset (input, active Low). Asynchronous reset signal.
A Low level on this pin generates an internal reset signal.
The /RES signal must be kept Low for at least one clock
cycle. The CPU pushes the contents of the PC onto the
stack and then fetches a new Program Counter (PC) value
from program memory address 0FFCH after the Reset
signal is released. RES Low tri-states the PA and PD bases.
/ROMEN ROM Enable (input). An active Low signal enables
the internal ROM. Program execution begins at 0000H
from the ROM. An active High input disables the ROM and
external fetches occur from address 0000H.
/RDYE Data Ready (input). User-supplied Data Ready
signal for data to and from external data bus. This pin
stretches the /EI and ER//W lines and maintains data on the
address bus and data bus. The ready signal is sampled
from the rising edge of the clock with appropriate setup
and hold times. The normal write cycle will continue from
the next rising clock only if ready is active.
UI1-UI0 Two Input Pins (input). General purpose input
pins. These input pins are directly tested by the conditional
branch instructions. These are asynchronous input signals
that have no special clock synchronization requirements.
UO1-UO0 Two Output Pins (output). General purpose
output pins. These pins reflect the inverted value of status
register bits S5 and S6. These bits may be used to output
data by writing to the status register.
ADDRESS SPACE
Program Memory. Programs of up to 4K words can be
masked into internal ROM. Four locations are dedicated to
the vector address for the three interrupts (0FFDH-0FFFH)
and the starting address following a Reset (0FFCH). Internal
ROM is mapped from 0000H to 0FFFH, and the highest
location for program is 0FFBH. If the /ROMEN pin is held
High, the internal ROM is inactive and the processor
executes external fetches from 0000H to FFFFH. In this
case, locations FFFC-FFFF are used for vector addresses.
Internal Data RAM. The Z89C00 has an internal 512 x
16-bit word data RAM organized as two banks of 256 x
16-bit words each, referred to as RAM0 and RAM1. Each
data RAM bank is addressed by three pointers, referred to
as Pn:0 (n = 0-2) for RAM0 and Pn:1 (n = 0-2) for RAM1. The
RAM addresses for RAM0 and RAM1 are arranged from
0-255 and 256-511, respectively. The address pointers,
which may be written to or read from, are 8-bit registers
connected to the lower byte of the internal 16-bit D-Bus
and are used to perform no overhead looping. Three
addressing modes are available to access the Data RAM:
register indirect, direct addressing, and short form direct.
These modes are discussed in detail later. The contents of
the RAM can be read or written in one machine cycle per
word without disturbing any internal registers or status
other than the RAM address pointer used for each RAM.
The contents of each RAM can be loaded simultaneously
into the X and Y inputs of the multiplier.
Registers. The Z89C00 has 12 internal registers and up to
an additional eight external registers. The external registers
are user definable for peripherals such as A/D or D/A or to
DMA or other addressing peripherals. External registers
are accessed in one machine cycle the same as internal
registers.
DC 4083-00
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Z89C00 arduino
ZILOG
INSTRUCTION FORMAT
PRELIMINARY
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z89C00
16-BIT DIGITAL SIGNAL PROCESSOR
Note:
Source/Destination fields can specify either register or
RAM addresses in RAM pointer indirect mode.
Figure 8. General Instruction Format
Source field
Destination field
RAM Bank selection
Opcode
A. Registers
Source/Destination
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Register
BUS**
X
Y
A
SR
STACK
PC
P**
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
B. Register Pointers Field
Source/Destination
Meaning
00xx
01xx
10xx
11xx
NOP
+1
–1/LOOP
+1/LOOP
xx00
xx01
xx10
xx11
P0:0 or P0:1*
P1:0 or P1:1*
P2:0 or P2:1*
Short Form Direct
Mode
Notes:
* If RAM Bank bit is 0, then Pn:0 are selected.
If RAM Bank bit is 1, then Pn:1 are selected.
** Read only.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Short Immediate Data
Reg. Pointer
0 0 0 P0:0
0 0 1 P1:0
0 1 0 P2:0
0 1 1 NA
1 0 0 P0:1
1 0 1 P1:1
1 1 0 P2:1
1 1 1 NA
Opcode
00011
Figure 9. Short Immediate Data Load Format
DC 4083-00
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