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PDF Z89303 Data sheet ( Hoja de datos )

Número de pieza Z89303
Descripción DIGITAL TELEVISION CONTROLLER
Fabricantes Zilog. 
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No Preview Available ! Z89303 Hoja de datos, Descripción, Manual

PRELIMINARY
Z89303/05/07
CPS DC-4222-03
PRELIMINARY
CUSTOMERPROCUREMENTSPECIFICATION
GENERAL DESCRIPTION
The Z89303/05/07 Digital Television Controllers are
application-specific controllers designed to provide
complete audio and video control of television receivers,
video recorders, with advanced on-screen display facilities.
The Z89303/05/07 are 24K, 16K and 12K ROM versions in
52-pin SDIP packages. The powerful 12 MHz Z89C00
RISC processor core allows the user to control the on-
board peripheral functions and registers using the standard
processor instruction set.
The extensive character attributes can be controlled in two
modes: by the on-screen display controller character
control mode for maximum display control flexibility, and
closed caption mode for optimum display of closed caption
text.
Closed caption text can be decoded directly from the
composite video signal with the assistance of the
processor's digital signal processing capabilities and
displayed on the screen. The character representation in
this mode allows for a simple attribute control through the
insertion of control characters, and each word of RAM
specifies two displayed characters.
The character control mode provides access to the full set
of attribute controls. Each word of RAM specifies a single
displayed character and basic character attributes, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that incude underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency. The 16-bit
display character representation allows the modification of
some key attributes on a character-by-character basis. A
character's pixel array is stored as a 16- or 18-word
representation in Character Graphics ROM (CGROM).
The ROM contents are referenced by a 16-bit word stored
in video RAM (VRAM) defining the character type and its
key attributes.
Z89303/05/07
DIGITALTELEVISIONCONTROLLER
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry standard I2C port.
Additional hardware provides the capability to display two
times normal size characters. The smoothing logic
contained in the on-screen display circuit improves the
appearance of larger fonts. Fringing circuitry can be
activated to improve the visibiity of text by surrounding the
character lines with a one-pixel border.
RGB outputs provide the direct video signals, and a
blanking output is provided to control the video multiplexor.
Dot clock and verticle line synchronization are normally
obtained from H_FLYBACK and V_FLYBACK, but can be
generated by the Z89303/05/047, and driven to the external
deflection unit through the bidirectional SYNC ports when
external video synchronization signals are not present.
User control can be monitored through the keypad scanning
port, or the 16-bit remote control capture register. Receiver
functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
All nine PWM ports are available in the 52-pin package.
The Z89303/05/07 has two internal 12 MHz VCOs that are
referenced to a 32 KHz internal oscillator to provide the
system clock. In Sleep mode, the controller uses the 32
KHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP mode when main power is not available for
minimal power consumption.
DC-4222-03 (10-10-94)
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Z89303 pdf
PRELIMINARY
V1, V2, V3 ANALOG OUTPUT
Specifications V = 5.25 V
CC
VCC = 5.25 V
Output Voltage
Settling Time
Condition
Bit = 11
Bit = 10
Bit = 01
Bit = 00
70% of DC Level, 10pf Load
Z89303/05/07
CPS DC-4222-03
Limit
4.55 V +/– 0.25 V
3.205V +/– 0.2 V
1.95 V +/– 0.15 V
0.65 V +/– 0.1 V
< 50 nsec
V1, V2, V3 ANALOG OUTPUT
Specifications VCC = 4.75V
VCC = 4.75V
Output Voltage
Settling Time
Condition
Bit = 11
Bit = 10
Bit = 01
Bit = 00
70% of DC Level, 10pf Load
Limit
3.90 V +/– 0.25 V
2.90 V +/– 0.2 V
1.90 V +/– 0.15 V
0.1 V +/– 0.1 V
< 50 nsec
Z893XX
32K Oscillator Recommended Circuit
Notes:
c) PWM[8,7] is not available on the 40-pin DIP version.
d) Port0[F:A] is not available on the 40-pin DIP version.
e) Port19 is not available on the 40-pin DIP version.
f) SCL I/O pin is shared with Port0 or Port11.
g) SCD I/O pin is shared with Port02 or Port12.
h) Half Blank output is a function shared with Port0F.
Half Blank output is not available on the 40-pin DIP version.
i) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
k) Internal processor SCLK is shared with Port16.
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