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PDF Z87L00 Data sheet ( Hoja de datos )
| Número de pieza | Z87L00 | |
| Descripción | Spread Spectrum Controllers | |
| Fabricantes | Zilog. | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de Z87L00 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY PRODUCT SPECIFICATION
1
Z87000/Z87L00
1
SPREAD SPECTRUM CONTROLLERS
FEATURES
ROM RAM* I/O
Device (KWords) (Words) Lines
Z87000
12
512 32
Z87L00
12
512
Note: *General-Purpose
32
Package
Information
84-Pin PLCC
100-Pin QFP
100-Pin QFP
s Transceiver/Controller Chip Optimized for Implement-
ation of 900 MHz Spread Spectrum Cordless Phone
– Adaptive Frequency Hopping
– Transmit Power Control
– Error Control Signaling
– Handset Power Management
– Support of 32 kbps ADPCM Speech Coding for
High Voice Quality
s DSP Core Acts as Phone Controller
– Zilog-Provided Embedded Transceiver Software to
Control Transceiver Operation and Base Station-
Handset Communications Protocol
– User-Modifiable Software Governs Phone
Features
s Transceiver Circuitry Provides Primary Cordless Phone
Communications Functions
– Digital Downconversion with Automatic Frequency
Control (AFC) Loop
– FSK Demodulator
– FSK Modulator
– Symbol Synchronizer
– Time Division Duplex (TDD) Transmit and Receive
Buffers
s On-Chip A/D and D/A to Support 10.7 MHz IF Interface
s Bus Interface to Z87010 ADPCM Processor
s Static CMOS for Low Power Consumption
s 3.0V to 3.6V, -20°C to +70°C, Z87L00
4.5V to 5.5V, -20°C to +70°C, Z87000
s 16.384 MHz Base Clock
GENERAL DESCRIPTION
The Z87000/Z87L00 FHSS Cordless Telephone Trans-
ceiver/Controllers are expressly designed to implement a
900 MHz frequency hopping spread spectrum cordless
telephone compliant with United States FCC regulations
for unlicensed operation. The Z87000 and Z87L00 are dis-
tinct 5V and 3.3V versions, respectively, of the device. For
the sake of brevity, all subsequent references to the
Z87000 in this document also apply to the Z87L00, unless
specifically noted.
The Z87000 supports a specific cordless phone system
design that uses frequency hopping and digital modulation
to provide extended range, high voice quality, and low sys-
tem costs.The Z87000 uses a Zilog 16-bit fixed-point two’s
complement static CMOS Digital Signal Processor core as
the phone and RF section controller. The Z87000’s DSP
core processor further supports control of the RF section’s
frequency synthesizer for frequency hopping and the gen-
eration of the control messages needed to coordinate in-
corporation of the phone’s handset and base station.
DS96WRL0501
PRELIMINARY
1-1
1 page  
Zilog
Pin Number
1,19,27,36,46,
56,63,75
2
3,23,31,41,51,
61,71,79
4
5
6
7
8,13
9
10
11,15
12
14
16
17
18,20,21,22,24,
25,26,28,29,30,
32,33,34,35,37,38
59,60
62
64
65
76
77
78
80,81,82
83
84
Table 1. 84-Pin PLCC Pin Description Summary
Symbol
GND
Ground
Function
Z87000/Z87L00
Spread Spectrum Controllers
Direction
–
1
MCLK
VDD
RFTX
SYLE
RXON
RFRX
AGND
PWLV
RSSI
AVDD
TX
RX
VREF
RFEON
P115
Master clock (16.384 MHz)
Digital
Input
–
RF transmit switch control
RF synthesizer load enable
Demodulator “on” indication
RF receive switch control
Analog ground
RF transmit power level
RF receive signals strength indicator
Analog VDD
Analog transmit IF signal
Analog receive IF signal
Analog reference voltage for RX signal
RF module on/off control
General-purpose
Output
Output
Output
Output
–
Output
Input
–
Output
Input
Output
Output
Input
ANT1
TEST
HBSW
CLKOUT
VXRDYB
VXSTRB
VXRWB
VXADD2
CODCLK
/RESETB
RF diversity antenna control
Main test mode control
Handset/Base Control
Clock output to ADPCM Processor
ADPCM processor ready signal
ADPCM processor data strobe
ADPCM read/write control
ADPCM processor address bus
Clock output to codec
Reset signal
Input/Output
Input
–
Output
Output
Input
Input
Input
Output
Input
DS96WRL0501
PRELIMINARY
1-5
5 Page 
Zilog
Z87000/Z87L00
Spread Spectrum Controllers
ANALOG CHARACTERISTICS
Table 7. 1-Bit ADC (Temperature: -20/+70°C)
Parameter
Minimum
Typical
Maximum
Resolution
Power dissipation
Power dissipation, Stop mode
Sample frequency
Sample window(1)
Bandwidth
Supply Range(=AVDD)
Z87L00
Z87000
Acquisition time
Settling time
Conversion time
Aperture delay
Aperture uncertainty(2)
Input voltage range (p-p)
Reference voltage
Z87L00
Z87000
Input resistance
Input capacitance
-
0.54
(70°c)
0.06
(70°c)
-
29
-
1
1.0
(40°c)
0.2
(40°c)
8.192
31
60
-
2.75
(-20°c)
1.1
(-20°c)
-
33
-
3.0 3.6
4.5 5.5
23
8
8 10
18
46
18
2 3 8.5
- - 0.5
800 1000 1200
1.7 (AVDD= 3V) 1.9 (AVDD= 3.3V) 2.1 (AVDD= 3.6V)
2.7 (AVDD=4.5V) 3.0 (AVDD= 5V) 3.3 (AVDD= 5.5V)
10 18
25
- 10
-
Notes:
Window of time while input signal is applied to sampling capacitor; see next figure.
Uncertainty in sampling time due to random variations such as thermal noise.
Units
bit
mW
mW
MHz
ns
MHz
V
V
ns
ns
ns
ns
ns
mV
V
V
KOhm
pF
1
DS96WRL0501
PRELIMINARY
1-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Z87L00.PDF ] | |
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