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PDF Z86247 Data sheet ( Hoja de datos )

Número de pieza Z86247
Descripción 40-PIN LOW-COST DIGITAL TELEVISION CONTROLLER (4LDTC)
Fabricantes Zilog. 
Logotipo Zilog. Logotipo



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Z86247
CPS DC-9027-00
PRELIMINARY
CUSTOMERPROCUREMENTSPECIFICATION
GENERAL DESCRIPTION
The Z86247 40-pin Low-Cost Digital Television Controller
(4LDTC) introduces a new level of sophistication to single-
chip architecture. The Z86247 is a member of the Z8®
single-chip microcontroller family with 8 Kbytes of ROM
and 236 bytes of RAM. The device is offered in a 40-pin
package and is CMOS compatible. The 4LDTC offers
mask programmed ROM which enables the Z8
microcontroller to be used in a high volume production
application device embedded with a custom program
(customer supplied program) and combines together with
the Z86C27 (DTC) and Z86127 (LDTC) to provide support
for high end, mid range and low end TV applications.
Zilog’s 4LDTC offers fast execution, efficient use of memory,
sophisticated interrupts, input/output bit manipulation
capabilities, and easy hardware/software system expansion
along with low cost and low power consumption. The
device provides an ideal performance and reliability solution
for consumer and industrial television applications.
The Z86247 architecture is characterized by utilizing Zilog’s
advanced Superintegration™ design methodology. The
device has an 8-bit internal data path controlled by a Z8
microcontroller and On Screen Display (OSD) logic circuits
and Pulse Width Modulators (PWM). On-chip peripherals
include two register mapped I/O ports (Ports 2 and Port 3),
interrupt control logic (one software, two external and three
internal interrupts) and a standby mode recovery input
port (Port 3, pin P30).
Z86247
40-PINLOW-COSTDIGITAL
TELEVISIONCONTROLLER(4LDTC)
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels. Three
8-bit PWM ports used to vary picture levels.
The 4LDTC applications demand powerful I/O capabilities.
The Z86247 fulfills this with 24 pins dedicated to input or
output. These lines are grouped into three ports, and are
configurable under software control to provide timing,
status signals, parallel I/O and an address/data bus for
interfacing to external memory.
There are three basic address spaces available to support
this wide range of configurations: Program Memory, Video
RAM, and Register File. The Register File is composed of
236 bytes of general purpose registers, two I/O Port
registers, 15 control and status registers and three reserved
registers.
To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the 4LDTC offers two on-chip counter/timers with a large
number of user selectable modes (Figure 1).
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
The OSD control circuits support 8 rows by 20 columns of
characters. The character color is specified by row. One of
the eight rows is assigned to show two kinds of colors for
bar type displays such as volume control. The OSD is
capable of displaying high resolution (11x15 dot pattern)
characters.
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
DC 9027-00 (7-27-94)
1

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Z86247 pdf
CAPACITANCE
TA=25°C;
V =GND=0V;
CC
Freq=1.0
MHz;
unmeasured
pins
to
GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
AFCIN input capacitance
Max Units
10 pF
20 pF
25 pF
10 pF
Z86247
CPS DC-9027-00
DC CHARACTERISTICS
TA=0°C to +70°C; VCC=+4.5V to +5.5V; FOSC=4 MHz
Sym Parameter
TA=0°C to +70°C Typical
Min Max @ 25°C Units Conditions
VIL Input Voltage Low
0
V Input XTAL/Osc In Low
ILC
V Input Voltage XTAL/Osc In High 0.7 V
IH CC
V Input XTAL/Osc In High
IHC
VHY Schmitt Hysteresis
V Maximum Pull-Up Voltage
PU
0.8 V
CC
0.1 VCC
VOL Output Voltage Low
V00-01
V
01-11
V
OH
AFC Level 01 In
AFC Level 11 In
Output Voltage High
I Reset Input Current
IR
I Input Leakage
IL
I Tri-State Leakage
OL
ICC Supply Current
ICC1
ICC2
Note:
[1] PWM open-drain
0.5 V
CC
V –0.4
CC
–3.0
–3.0
0.2 VCC
0.07 V
CC
V
CC
V
CC
12
0.4
0.4
0.45 VCC
0.75 V
CC
–80
3.0
3.0
20
6
10
1.48
0.98
3.2
3.0
0.8
0.16
0.19
1.9
3.12
4.75
–46
0.01
0.02
13.2
3.2
2.0
V
V External Clock Generator Driven
V External Clock Generator Driven
V External Clock Generator Driven
V
V [1]
V IOL=1.00 mA
V IOL=0.75 mA [1]
V
V
V I =–0.75 mA
OH
µA
V =0V
RL
µA
0V,V
CC
µA
0V,V
CC
mA All inputs at rail
mA All inputs at rail
µA All inputs at rail
5

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