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PDF Z86233 Data sheet ( Hoja de datos )

Número de pieza Z86233
Descripción CMOS Z8 8K ROM CONSUMER CONTROLLER PROCESSOR
Fabricantes Zilog. 
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Z86233/243
CP96DZ81201
CUSTOMER P ROCUREMENT S PECIFICA TION
FEATURES
ROM RAM
Part Kbytes bytes I/O
Package
Information
Z86233 8
Z86243 8
237 24 28-pinDIP,SOIC,PLCC
236 32 40-pin DIP,
44-pin PLCC,
44-pin QFP
s 3.0-to 5.5-Volt Operating Range
s Low-Power Consumption: 40 mW (Typical @5.0V)
s 0°C to +70°C Temperature Range
(–40°C to +105°C Temperature Range Available)
s Three Expanded Register File Control Registers
s Z86C33/C43 Pin and Package Compatible Version
(With Addition of 4K ROM)
Z86233/243
CMOS Z8® 8K ROM
CONSUMER CONTROLLER PROCESSOR
s 32 Input/Output Lines (Three with Comparator Inputs)
(Z86243 Only)
s Vectored, Prioritized Interrupts with Programmable
Polarity
s Two Comparators
s Two Programmable 8-Bit Counter/Timers, Each
with a 6-Bit Programmable Prescaler
s Watch-Dog Timer (WDT)/Power-On Reset (POR)
s On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
s RAM and ROM Protect
s Clock Free Watch-Dog Timer (WDT) Reset
GENERAL DESCRIPTION
The Z86233/243 Consumer Controller Processor is a
member of Zilog's Z8® single-chip microcontroller family
featuring enhanced wake-up circuitry, programmable
Watch-Dog timers and low-EMI options. The parts
provide flexible and efficient growth paths for designers
currently using the 4K ROM versions of the consumer
controller devices (Z86C30/C40/C33/C43).
Four address spaces, the Program Memory, Register File,
Data Memory and Expanded Register File (ERF), support
a wide range of memory configurations. Through the ERF,
the designer has access to two additional control registers
which provide extra peripheral devices, I/O ports, and
register addresses.
For applications demanding powerful I/O capabilities, the
Z86243 provides 32 pins dedicated to input and output.
The Z86233 provides 24 pins dedicated to input and
output. These lines are grouped into four ports with eight
lines each, and are configurable under software control to
provide timing, status signals, or parallel I/O.
With ROM/ROMless selectivity, the Z86243 provides both
external memory and pre-programmed ROM, which en-
ables this Z8 microcontroller to be used in high-volume
applications, or where code flexibility is required.
Note: All Signals with a preceding front slash, "/", are active
Low, e.g., B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
CP96DZ81201 (8/96)
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Z86233 pdf
P21
P22
P23
P24
/DS
NC
R//W
P25
P26
P27
P04
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 Z86243 34
PLCC
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P30
P36
P37
P35
/RESET
R//RL
/AS
P34
P33
P32
P31
Z86233/243
CP96DZ81201
44-Pin PLCC Pin Configuration
Pin #
1
2
3-4
5
6-10
11
12
13
14-16
17-19
20-21
22
23
24
25-26
Symbol
GND
GND
P12-P13
P03
P20-P24
/DS
N/C
R//W
P25-P27
P04-P06
P14-P15
P07
VCC
VCC
P16-P17
44-Pin PLCC Pin Identification
Function
Direction
Ground
Ground
Port 1, Pins 2,3
Port 0, Pin 3
Port 2, Pins 0,1,2,3,4
In/Output
In/Output
In/Output
Data Strobe
Not Connected
Read/Write
Port 2, Pins 5,6,7
Port 0, Pins 4,5,6
Output
Output
In/Output
In/Output
Port 1, Pins 4,5
Port 0, Pin 7
Power Supply
Power Supply
Port 1, Pins 6,7
In/Output
In/Output
In/Output
Pin #
27
28
29-31
32
33
34
35
36
37
38
39
40-41
42-43
44
Symbol
XTAL2
XTAL1
P31-P33
P34
/AS
R//RL
/RESET
P35
P37
P36
P30
P00-P01
P10-P11
P02
Function
Direction
Crystal Oscillator
Crystal Oscillator
Port 3, Pins 1,2,3
Port 3, Pin 4
Address Strobe
Output
Input
Input
Output
Output
ROM/ROMless select Input
Reset
Input
Port 3, Pin 5
Output
Port 3, Pin 7
Output
Port 3, Pin 6
Output
Port 3, Pin 0
Port 0, Pins 0,1
Port 1, Pins 0,1
Port 0, Pin 2
Input
In/Output
In/Output
In/Output
CP96DZ81201 (8/96)
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Z86233 arduino
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
(SCLK/TCLK = XTAL/2)
Z86233/243
CP96DZ81201
No Symbol
1 TdA(AS)
2 TdAS(A)
Parameter
Address Valid to /AS Rise Delay
/AS Rise to Address Float Delay
TA = 0°C to +70°C
Note [3] 12 MHz 16 MHz
VCC Min Max Min Max
3.0 35
5.5 35
3.0 45
5.5 45
25
25
35
35
TA = –40°C to +105°C
12 MHz 16 MHz
Min Max Min Max Units Notes
35 25
35 25
45 35
45 35
ns [2]
ns [2]
ns
3 TdAS(DR)
4 TwAS
/AS Rise to Read Data Req’d Valid
/AS Low Width
3.0 250 180
250 180 ns [1,2]
5.5 250 180
250 180 ns
3.0 55
40
55 40
ns [2]
5.5 55
40
55 40
ns
5 Td
6 TwDSR
Address Float to /DS Fall
/DS (Read) Low Width
3.0 0
5.5 0
3.0 200
5.5 200
0
0
135
135
00
00
200 135
200 135
ns
ns
ns [1,2]
ns
7 TwDSW
/DS (Write) Low Width
8 TdDSR(DR) /DS Fall to Read Data Req’d Valid
3.0 110
80
5.5 110
80
3.0 150
5.5 150
75
75
110
110
150
150
80
80
75
75
ns [1,2]
ns
ns [1,2]
ns
9 ThDR(DS)
10 TdDS(A)
Read Data to /DS Rise Hold Time
/DS Rise to Address Active Delay
3.0 0
5.5 0
3.0 45
5.5 55
0
0
50
50
00
00
45 50
55 50
ns [2]
ns
ns [2]
ns
11 TdDS(AS) /DS Rise to /AS Fall Delay
12 TdR/W(AS) R//W Valid to /AS Rise Delay
3.0 30
5.5 45
3.0 45
5.5 45
35
35
25
25
30 35
45 55
45 25
45 25
ns [2]
ns
ns [2]
ns
13 TdDS(R/W) /DS Rise to R//W Not Valid
3.0
5.5
14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0
5.5
45
45
55
55
35
35
25
25
45 35
45 35
55 25
55 25
ns [2]
ns
ns [2]
ns
15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 3.0 45
35
45 35
ns [2]
5.5 55
35
55 35
ns
16 TdA(DR) Address Valid to Read Data Req’d Valid 3.0 310 230
310 230 ns [1,2]
5.5 310 230
310 230 ns
17 TdAS(DS)
18 TdDI(DS)
/AS Rise to /DS Fall Delay
Data Input Setup to /DS Rise
3.0 65
5.5 65
3.0 115
5.5 75
45
45
60
60
65 45
65 45
115 60
75 60
ns [2]
ns
ns [1,2]
ns
19 TdDM(AS) /DM Valid to /AS Rise Delay
3.0 35
5.5 35
30
30
35 30
35 30
ns [2]
ns
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] The VDD voltage specification of 3.0V guarantees 3.3V ± 0.3V, and
the VDD voltage specification of 5.5V guarantees 5.0V ±0.5V.
Standard Test Load
All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
CP96DZ81201 (8/96)
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