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PDF Z86127 Data sheet ( Hoja de datos )
| Número de pieza | Z86127 | |
| Descripción | LOW-COST DIGITAL TELEVISION CONTROLLER (LDTC) | |
| Fabricantes | Zilog. | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de Z86127 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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CUSTOMER PROCUREMENT SPECIFICATION
GENERAL DESCRIPTION
The Z86127 Low-Cost Digital Television Controller (LDTC)
introduces a new level of sophistication to single-chip
architecture. The Z86127 is a member of the Z8® single-
chip microcontroller family with 8 Kbytes of ROM and 236
bytes of RAM. The device is housed in a 64-pin DIP
package, in which only 52 are active, and are CMOS
compatible. The LDTC offers mask programmed ROM
which enables the Z8 microcontroller to be used in a high
volume production application device embedded with a
custom program (customer supplied program).
Zilog’s LDTC offers fast execution, efficient use of memory,
sophisticated interrupts, input/output bit manipulation
capabilities, and easy hardware/software system expansion
along with low cost and low power consumption. The
device provides an ideal performance and reliability solution
for consumer and industrial television applications.
The Z86127 architecture is characterized by utilizing Zilog’s
advanced Superintegration™ design methodology. The
device has an 8-bit internal data path controlled by a Z8
microcontroller and On Screen Display (OSD) logic circuits/
Pulse Width Modulators (PWM). On-chip peripherals
include two register mapped I/O ports (Ports 2 and Port 3),
interrupt control logic (one software, two external and three
internal interrupts) and a standby mode recovery input
port (Port 3, pin P30).
The OSD control circuits support 8 rows by 20 columns of
characters. The character color is specified by row. One of
the eight rows is assigned to show two kinds of colors for
bar type displays such as volume control. The OSD is
capable of displaying either low resolution (5x7 dot pattern)
or high resolution (11x15 dot pattern) characters. The
Z86C97 currently supports high resolution characters only.
Z86127
LOW-COST DIGITAL
TELEVISION CONTROLLER (LDTC)
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels. Five 8-bit
PWM ports are used to vary picture levels.
The LDTC applications demand powerful I/O capabilities.
The Z86127 fulfills this with 27 I/O pins dedicated to input
and output. These lines are grouped into four ports, and
are configurable under software control to provide timing,
status signals, parallel I/O and an address/data bus for
interfacing to external memory.
There are three basic address spaces available to support
this wide range of configurations: Program Memory, Video
RAM, and Register File. The Register File is composed of
236 bytes of general purpose registers, two I/O Port
registers, 15 control and status registers and three reserved
registers.
To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the LDTC offers two on-chip counter/timers with a large
number of user selectable modes (Functional Block
Diagram).
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
V
SS
DC-4063-00 (10-16-91)
1
1 page  
DC CHARACTERISTICS
TA=0°C to +70°C; VCC=+4.5V to +5.5V; FOSC=4 MHz
Sym Parameter
TA=0°C to +70°C Typical Units Conditions
Min Max @ 25°C
VIL Input Voltage Low
0
VILC Input XTAL/Osc In Low
V Input Voltage XTAL/Osc In High 0.7 V
IH CC
VIHC Input XTAL/Osc in High
VHY Schmitt Hysteresis
V Maximum Pull-up Voltage
PU
0.8 VCC
0.1 VCC
VOL Output Voltage Low
V00-01
V01-11
V
OH
IIR
I
IL
IOL
ICC
I
CC1
ICC2
AFC Level 01 In
AFC Level 11 In
Output Voltage High
Reset Input Current
Input Leakage
Tri-State Leakage
Supply Current
Notes:
[1] Port 5
[2] PWM open drain
0.5 VCC
V -0.4
CC
-3.0
-3.0
0.2 VCC
0.07 VCC
V
CC
VCC
12
0.4
0.4
0.4
1.5
0.45 VCC
0.75 VCC
-80
3.0
3.0
20
6
10
1.48
0.98
3.2
3.0
0.8
0.16
0.19
0.19
1.00
1.9
3.12
4.75
-46
0.01
0.02
13.2
3.2
0
V
V External Clock Generator Driven
V External Clock Generator Driven
V External Clock Generator Driven
V
V [2]
V IOL=1.00mA
V I =3.2mA, [1]
OL
V IOL=0.75mA [2]
V I =10mA [1]
OL
V
V
V I =-0.75mA
OH
µA VRL=0V
µA
0V,V
CC
µA 0V,VCC
mA All inputs at rail
mA All inputs at rail
µA All inputs at rail
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet Z86127.PDF ] | |
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