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PDF Z80185 Data sheet ( Hoja de datos )

Número de pieza Z80185
Descripción Z8018x Family MPU
Fabricantes Zilog. 
Logotipo Zilog. Logotipo



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Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
PRELIMINARY PRODUCT SPECIFICATION
FEATURES
Part
Z80185
Z80195
ROM
(KB)
32 x 8
0
UART
Baud Rate
512 Kbps
512 Kbps
s 100-Pin QFP Package
s 5.0-Volt Operating Range
s Low-Power Consumption
s 0°C to +70°C Temperature Range
Speed
(MHz)
20, 33
20, 33
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
s Enhanced Z8S180 MPU
s Four Z80 CTC Channels
s One Channel ESCCController
s Two 8-Bit Parallel I/O Ports
s Bidirectional Centronics Interface (IEEE 1284)
s Low-EMI Option
GENERAL DESCRIPTION
The Z80185 and Z80195 are smart peripheral controller
devices designed for general data communications appli-
cations, and architected specifically to accommodate all
input and output (I/O) requirements for serial and parallel
connectivity. Combining a high-performance CPU core
with a variety of system and I/O resources, the Z80185/195
are useful in a broad range of applications. The Z80195 is
the ROMless version of the device.
The Z80185 and Z80195 feature an enhanced Z8S180
microprocessor linked with one enhanced channel of the
Z85230 ESCCserial communications controller, and 25
bits of parallel I/O, allowing software code compatibility
with existing software code.
Seventeen lines can be configured as bidirectional
Centronics (IEEE 1284) controllers. When configured as a
1284 controller, an I/O line can operate in either the host or
peripheral role in compatible, nibble, byte or ECP mode. In
addition, the Z80185 includes 32 Kbytes of on-chip ROM.
These devices are well-suited for external modems using
a parallel interface, protocol translators, and cost-effective
WAN adapters. The Z80185/195 is ideal for handling all
laser printer I/O, as well as the main processor in cost-
effective printer applications.
Notes:
All Signals with a preceding front slash, "/", are active Low.
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
V
CC
GND
V
DD
VSS
DS971850301
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Z80185 pdf
Zilog
PRELIMINARY
DC CHARACTERISTICS
V
DD
=
5.0V
± 10%,
V
SS
=
0V
over
specified
temperature
range,
unless
otherwise
noted.
Symbol
Item
Condition
VIH Input “H” Voltage
VIL Input “L” Voltage
V Output “H” Voltage
OH
V Output “L” Voltage
OL1
IIL Input Leakage
VIN=0.5 to
Current All Inputs
VDD–0.5
Except XTAL,EXTAL
I Tri-State Leakage
TL
Current
V =0.5 to
IN
V –0.5
DD
V Supply Current*
DD
Normal Operation
For 5.0V:
For 5.0V:
f = 20 MHz
f = 33 MHz
ICC* Power Dissipation*
System Stop Mode
For 5.0V: f = 20 MHz
For 5.0V: f = 33 MHz
Notes:
† See Class Reference Table
* VIH min = VDD –1.0V, VIL max = 0.8V (All output terminals are at no load.)
Min. Typ.
60
68
5
7
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Max.
Unit
V
V
V
V
1.0
µA
1.0 µA
120 mA
132 mA
10 mA
13 mA
DS971850301
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Z80185 arduino
Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
/MREQ
63
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
/RAMCS
/ROMCS
/IORQ
/IOCS
64
Figure 11. /ROMCS and /RAMCS Timing
EXTAL
VIL1
51 52
VIH1
VIH1
VIL1
Figure 12. External Clock Rise Time
and Fall Time
56 55
Figure 13. Input Rise and Fall Time
(Except EXTAL, /RESET)
DS971850301
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