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PDF Z8018110FEC Data sheet ( Hoja de datos )

Número de pieza Z8018110FEC
Descripción SMART ACCESS CONTROLLER (SAC)
Fabricantes Zilog. 
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Zilog
Z80181
SMART ACCESS CONTROLLER SAC
PRELIMINARY PRODUCT SPECIFICATION
FEATURES
Z80181
SMART ACCESS CONTROLLER (SAC)
s Z80180 Compatible MPU Core with 1 Channel of
Z85C30 SCC, Z80 CTC, Two 8-Bit General-Purpose
Parallel Ports, and Two Chip Select Signals.
s High Speed Operation (10 MHz)
s Low Power Consumption in Two Operating Modes:
- (TBD) mA Typ. (Run Mode)
- (TBD) mA Typ. (STOP Mode)
s Wide Operational Voltage Range (5V ± 10%)
s TTL/CMOS Compatible
s Clock Generator
s One Channel of Z85C30 Serial Communication
Controller (SCC)
s Z180 Compatible MPU Core Includes:
- Enhanced Z80 CPU Core
- Memory Management Unit (MMU) Enables Access
to 1MB of Memory
- Two Asynchronous Channels
- Two DMA Channels
- Two 16-Bit Timers
- Clocked Serial I/O Port
s On-Board Z84C30 CTC
s Two 8-Bit General-Purpose Parallel Ports
s Memory Configurable RAM and ROM Chip Select Pins
s 100-Pin QFP Package
GENERAL DESCRIPTION
The Z80181 SACSmart Access Controller (hereinafter,
referred to as Z181 SAC) is a sophisticated 8-bit CMOS
microprocessor that combines a Z180-compatible MPU
(Z181 MPU), one channel of Z85C30 Serial Communica-
tion Controller (SCC), a Z80 CTC, two 8-bit general-pur-
pose parallel ports, and two chip select signals, into a
single 100-pin Quad Flat Pack (QFP) package (Figures 1
and 2). Created using Zilog's patented Superintegration
methodology of combining proprietary IC cores and cells,
this high-end intelligent peripheral controller is well-suited
for a broad range of intelligent communication control
applications such as terminals, printers, modems, and
slave communication processors for 8-, 16- and 32- bit
MPU based systems.
Information on enhancement/cost reductions of existing
hardware using Z80/Z180 with Z8530/Z85C30 applica-
tions is also included in this product specification.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
V
CC
GND
V
DD
VSS
DS971800500
2-1

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Z8018110FEC pdf
Zilog
Pin Name
/INT0
Pin Number
100
Input/Output, Tri-State
Wired-OR I/O, Active 0
/INT1,
/INT2
1, 2,
In, Active 0
/NMI
99
/HALT
81
In, Active 0
Out, tri-state, Active 0
/BUSREQ 97
In, Active 0
/BUSACK 96
/WAIT
95
Out, Active 0
Wired-OR I/O, Active 0
Z80181
SMART ACCESS CONTROLLER SAC
Function
Maskable Interrupt Request 0. Interrupt is generated by
peripheral devices. This signal is accepted if the interrupt
enable Flip-Flop (IFF) is set to “1”. Internally, the SCC and
CTC’s interrupt signals are connected to this line, and
require an external pull-up resistor.
Maskable Interrupt Request 1 and 2. This signal is
generated by external peripheral devices. The CPU hon-
ors these requests at the end of current instruction cycle as
long as the /NMI, /BUSREQ and /INT0 signals are inactive.
The CPU will acknowledge these interrupt requests with an
interrupt acknowledge cycle. Unlike the acknowledgment
for /INT0, during this cycle, neither /M1 or /IORQ will
become active.
Non-Maskable Interrupt Request Signal. This interrupt
request has a higher priority than the maskable interrupt
request and does not rely upon the state of the interrupt
enable Flip-Flop (IFF).
Halt Signal. This signal is asserted after the CPU has
executed either the HALT or SLP instruction, and is waiting
for either non-maskable interrupt maskable interrupt be-
fore operation can resume. It is also used with the /M1 and
ST signals to decode the status of the CPU machine cycle.
BUS Request Signal. This signal is used by external
devices (such as a DMA controller) to request access to
the system bus. This request has higher priority than /NMI
and is always recognized at the end of the current machine
cycle. This signal will stop the CPU from executing further
instructions and place the address bus, data bus, /MREQ,
/IORQ, /RD and /WR signals into the high impedance state.
/BUSREQ is normally wired-OR and a pull-up resistor is
externally connected.
Bus Acknowledge Signal. In response to /BUSREQ sig-
nal, /BUSACK informs a peripheral device that the address
bus, data bus, /MREQ, /IORQ, /RD and /WR signals have
been placed in the high impedance state.
Wait Signal. /WAIT informs the CPU that the specified
memory or peripheral is not ready for a data transfer. As
long as /WAIT signal is active, the MPU is continuously kept
in the wait state. Internally, the /WAIT signal from the SCC
interface logic is connected to this line, and requires an
external pull-up resistor.
DS971800500
2-5

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Z8018110FEC arduino
Zilog
Z80181
SMART ACCESS CONTROLLER SAC
Pin Name
IEI
Pin Number
62
Input/Output, Tri-State
In, Active 1
IEO 60
Out, Active 1
/ROMCS 61
/RAMCS 30
/RESET
98
EXTAL
94
Out, Active 0
Out, Active 0
In, Active 0
In, Active 1
XTAL
PHI
E
TEST
V
CC
VSS
93 Out
90 Out, Active 1
86 Out, Active 1
73
39, 82
18, 40, 59,
63, 92
Out
Function
Interrupt enable input signal. IEI is used with the IEO to
form a priority daisy chain when there is more than one
interrupt-driven peripheral.
The interrupt enable output signal. In the daisy-chain
interrupt control, IEO controls the interrupt of external
peripherals. IEO is active when IEI is “1” and the CPU is not
servicing an interrupt from the on-chip peripherals.
ROM Chip select. Used to access ROM. Refer to “Func-
tional Description” on chip select signals for further expla-
nation.
RAM Chip Select. Used to access RAM. Refer to “Func-
tional Description” on chip select signals for further expla-
nation.
Reset signal. /RESET signal is used for initializing the MPU
and other devices in the system. It must be kept in the
active state for a period of at least 3 system clock cycles.
Crystal oscillator connecting terminal. A parallel reso-
nant crystal is recommended. If an external clock source
is used as the input to the Z180 Clock Oscillator unit,
supply the clock into this terminal.
Crystal oscillator connecting terminal.
System Clock. Single-phase clock output from Z181
MPU.
Enable Clock. Synchronous Machine cycle clock output
during a bus transaction.
Test pin. Used in the open state.
Power Supply. +5 Volts
Power Supply. 0 Volts
DS971800500
2-11

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