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PDF YGV619 Data sheet ( Hoja de datos )
| Número de pieza | YGV619 | |
| Descripción | Advanced Video Display Processor 6 | |
| Fabricantes | LSI Computer Systems | |
| Logotipo |  |
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YGV619
AVDP6
Advanced Video Display Processor 6
s Outline
YGV619 is a VDP (Video Display Processor) adopting OSD display control system which is best suited to the
data broadcasting. The digital image interface of this device for connection with MPEG decoder has been
improved. The use of this device allows screen composition that is suited to mobile information terminals, car
navigation system, etc. Scan timing conforming to the display standard of digital TVs can be made.
Two built-in PLL circuits allows to realize superimposition of external image signal on original image signal,
and to produce clock best suited to SDRAM that is adopted as external video memory.
s Features
q Display planes: External digital image is overlaid with OSD images composed of regions.
Up to four planes, which are individually composed of back drop plane (plane on which external images are inputted)
+ region, are available.
q OSD image format:
8bit/dot palette mode, and 16 bit RGB or YCbCr format can be selected.
YCbCr conforms to the conversion method of ITU601.
Color palette (256 colors in 16777 k colors) can be specified by region.
q Digital image input format:
· 18bitR6G6B6
(Max. dot clock frequency: 80 MHz)
· 16bitYCbCr422 (Max. dot clock frequency: 80 MHz)
· 8bitITU656
(Dot clock frequency 27 MHz)
q Digital image output format:
· R6G6B6 + 2 bit AT
· 18bitYCbCr444 + 2 bit AT
· 16bitYCbCr422 + 2 bit AT
· 8bitITU656 + 2 bit AT + 6 bit α blending coefficient
q Max. OSD resolution: 960 dots × 1080 lines
(However, max. resolution of overlaid external image is 1920 ×1080 lines)
q Applicable digital TV image format:
· 525i
· 525p
· 1125i
q Video capture function:
· Draws external image input on the frame memory in real time.
· Can convert resolution.
· Provided with progressive scanning conversion
YGV619 CATALOG
CATALOG No.: LSI-4GV619A1
2001.01
1 page  
YGV619
s Pin Functions
< CPU INTERFACE >
l D31-0 (I/O: Pull Up)
CPU data bus. D31-16 pins are not used for 16 bit CPU (LWD=0). These pins are provided with a pull-up resistor.
Unused pins are to be open.
l A23-8 (I: Pull Up), A7-2 (I)
CPU address bus. When accessing CSREG space, signals inputted to A23-8 pins are ignored without regarding to the
bus width of CPU. Internal registers are selected depending on the state of signals inputted to A7-2 for 32 bit CPU or A7-
2 and A1 / WR3 pin for 16 bit CPU. Systems that control AVDP6 only with CSREG do not use this address bus.
However, A23-8 pins must be open because they are provided with pull-up resistor. All the addresses are valid when
accessing CSMEM space.
l CSREG (I)
Chip select signal input to REG space. Internal registers of AVDP6 are accessed by a using write / read pulse that is
inputted when the chip select signal is active.
When this signal is low, inputs to A23-8 pins are ignored.
l CSMEM (I)
CSMEM is made active when directly mapping the video memory connected to local bus of AVDP6 on the memory
space of CPU. The video memory managed by AVDP6 is directly accessed using write / read pulse that is inputted with
this chip select signal is active. The video memory can be accessed from REG space without using this pin, however, high
level signal must be inputted to CSMEM in this case.
l LWD (I: Pull Up)
Selects a CPU data bus width. When high level signal is inputted to this pin, AVDP6 operates as CPU 32 bit device, or
when low level signal is inputted to this pin, AVDP6 operates as CPU 16 bit device.
l A1 / WR3 , WR2-0 (I)
Controls write access to AVDP6 when chip select input signal is active. A1 / WR3 control D31-24, WR2 controls
D23-16, WR1 controls D15-8, and WR0 controls D7-0.
For 16 bit CPU, A1 / WR3 function as A1 of CPU address. WR2 is not used, and thus must be open because the pin is
provided with a pull-up resistor.
l RD (I)
Controls read access to AVDP6 when chip select input signal is active. D31-0 pins are in output state while this signal
and chip select signals are active. For 16 bit CPU, only D15-0 pins are in output state and D31-16 pins are in input states
at all times.
l WAIT (O: Pull Up, 3-state output)
Data wait signal output to CPU. When CSREG pin or CSMEM pin (hereafter called “CS pin”) is active, the WAIT
signal is asserted once for RD or A1 / WR3 and WR2-0 signals, and then negated when AVDP6 becomes accessible.
This pin becomes high impedance state when CS pin is not active, and outputs high level signal when CS pin is active
and RD or A1 / WR3 and WR2-0 pins are not active. Use this pin or READY depending on the type of CPU.
l READY (O: Pull Up, 3-state output)
Data ready signal output to CPU. When AVDP6 becomes accessible, this signal is asserted. This pin becomes high
impedance state when CS pin is not active, outputs high level signal when CS pin is active and RD or A1 / WR3,
WR2-0 pins are not active. Use this pin or WAIT depending on the type of CPU.
l INT (O)
Interrupt request signal output to CPU. This pin becomes active when internal state of AVDP6 coincides with the
setting conditions of the registers, and is reset when internal registers of AVDP6 are accessed.
5
5 Page 
YGV619
s Electrical Characteristics
Note!
The values of electrical characteristics shown in this section are target data, and do not
guarantee the specifications at the shipment of this product. The specification data
may be changed without prior notice. Therefore, please confirm the newest data when
using this product.
q Absolute maximum ratings
Items
Supply Voltage
Input Voltage*2
Input Voltage*3
Output Voltage*2
Output Current
Storage temperature
*1: Value with respect to VSS (GND) = 0V
*2: for no-tolerant pins
*3: for tolerant pins
Symbol
VDD*1
VI*1
VI*1
VO*1
IO
Tstg
Ratings
−0.5 to +4.6
−0.5 to VDD+ 0.5
−0.5 to 5.5
−0.5 to VDD+ 0.5
−20 to +20
−50 to +125
Unit
V
V
V
V
mA
°C
q Recommended operating conditions
Items
Supply Voltage
Low Level Input Voltage*2
High Level Input Voltage*2
Low Level Input Voltage*3
High Level Input Voltage*3
Low Level Input Voltage*4
High Level Input Voltage*4
Ambient operating temperature
Symbol
VDD*1
VIL*1
VIH*1
VIL*1
VIH*1
VIL*1
VIH*1
TOP
Min.
3.0
−0.3
2.0
−0.3
0.7VDD
−0.3
2.0
−45
*1: Value with respect to VSS (GND) = 0V
*2: when signal is inputted to I/O pins except DCIKN, SYCKIN and tolerant
*3: DCIKN, SYCKIN pins
*4: for tolerant pins
Typ.
3.3
Max.
3.6
0.8
VDD+ 0.3
0.3VDD
VDD+ 0.3
0.8
5.5
+85
Unit
V
V
V
V
V
V
V
°C
q Electrical characteristics under recommended operating conditions
l DC characteristics
Items
Low level output voltage (CMOS)
High level output voltage (CMOS)
Input leakage current
Output leakage current
Current consumption
*1: Measurement condition IOL=100µA
*2: Measurement condition IOH=-100µA
Symbol
VOL*1
VOH*2
ILI
ILO
IDD
Min. Typ.
2.4
Max.
0.4
10
25
Unit
V
V
µA
µA
mA
l Pin Capacitance
Items
Input Pin Capacitance
Output Pin Capacitance
I/O Pin Capacitance
Symbol
CI
CO
CIO
Min.
Typ.
Max.
8
10
12
Unit
pF
pF
pF
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet YGV619.PDF ] | |
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