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PDF XRT8001 Data sheet ( Hoja de datos )
| Número de pieza | XRT8001 | |
| Descripción | WAN Clock for T1 and E1 Systems | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XRT8001
WAN Clock for T1 and E1 Systems
GENERAL DESCRIPTION
The XRT8001 WAN Clock is a dual-phase-locked loop
chip that generates two very low jitter output clock
signals that can be used for synchronization clocks in
wide area networking systems. The XRT8001 has pre-
programmed multipliers and dividers that are selected
via the serial port. It generates two integer multiples of
8kHz, 56kHz, and 64kHz while locked onto an incom-
ing reference of 1.54MHz (T1), 2.048MHz (E1), 8kHz,
56kHz, or 64kHz
The XRT8001 WAN Clock can be configured to oper-
ate in one of six modes:
1. The Forward/Master Mode
2. The Reverse/Master Mode
3. The “Fractional T1/E1" Reverse/Master Mode
4. The “E1 to T1 - Forward/Master" Mode
5. The “High Speed - Reverse" Mode
6. The “Slave” Mode
FEATURES
• Dual Phased Locked Loops with
Pre-Programmed Multipliers and Dividers
• Pre-Programmed with Popular Frequency
Conversions for Communications Systems
October 2001-1
• Generates Output Clock Frequencies Ranging
From 8kHz up to 16.384MHz
• Serial Port Control for Optimal Performance
• Sync Output: 8kHz or 64kHz
• Low Jitter
• Cascadable (Master / Slave Modes)
• No External Components Needed
• Pin Compatible with the XRT8000
• Low Power (3.3V or 5V): 40 - 100mW
• - 40°C to +85°C Temperature Range
• 18-Lead PDIP or SOIC Packages
APPLICATIONS
• T1/E1 Access Equipment (DSU/CSU)
• Frame Relay Access Devices (FRAD)
• Basic Rate and Primary Rate ISDN Equipment
• ISDN Routers
• Terminals
• Remote Access Servers
• T1/E1 Concentrators
• T1/E1 Multiplexers
• T1/E1 Clock Rate Converters
• Internal Timing Generators
• System Synchronizers
3.3V or 5V
Reference Clock
8kHz to 16.384 MHz
Sync Out
8kHz or 64kHz
V CC
FIN
3
XRT8001
SYNC
2
CLK1 6
CLK2 13
Clock Output 1
Clock Output 2
Master/Slave
MSB
8
LOCKDET
11
CS SDO SDI SCLK
µC/µ P Serial I/O
PLL Lock Detect
Figure 1. System Diagram
ORDERING INFORMATION
Part Number
XRT8001IP
XRT8001ID
Package
18-Lead 300 Mil PDIP
18-Lead 300 Mil JEDEC SOIC
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
Rev. 1.01
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
ABSOLUTE MAXIMUM RATINGS
Supply Range ................................................ 7V
Voltage at any Pin ........... GND -0.3V to Vcc+0.3V
Operating Temperature................. - 40°C to +85°C
Storage Temperature ................... - 40°C to +85°C
Package Dissipation ............................... 500mW
XRT8001
DC ELECTRICAL CHARACTERISTICS (Except Microprocessor Serial Interface)1
Symbol
Parameter
Min. Typ. Max. Units
Condition
VIL Input Low Level
0.8 V
VIH Input High Level
2.0 V
VOL Output Low Level (CLK1, CLK2)
0.4 V
IOL = -6.0mA
VOH Output High Level (CLK1, CLK2)
2.4
V IOL = 6.0mA
VOL Output Low Level (LOCKDET, SYNC)
0.4 V
IOL = -3.0mA
VOH Output High Level (LOCKDET, SYNC) 2.4
V IOL = 3.0mA
IIL Input Low Current (CSB, MSB)
-150 mA
IIH Input High Current (CSB, MSB)
10 mA
VIN = VCC
IIL Input Low Current (except CSB, MSB) -10
mA
IIH Input High Current (except CSB, MSB)
10 mA
VIN = VCC
ICC Operating Current
11 30 mA 3.3V, No Load, CLk1, CLK2 = 8 x 2.048MHz
20 35 mA 5V, No Load, CLk1, CLK2 = 8 x 2.048MHz
RIN Internal Pull-up Resistance (CSB, MSB) 50 100 150 kW
Note:
1. 5V tolerant input considerations when operating from 3.3V:
When the XRT8001 is powered at 3.3V, it can tolerate 5V-level signals via its inputs. However, the user should be aware the XRT8001
contains a “Factory-Test” Mode. This mode is enabled whenever the MSB (Master-Slave select) input pin is pulled to about 2V above
VDD.
Therefore, if the user is powering the XRT8001 at 3.3V but is applying a 5.25V signal to the MSB input pin, then it is possible that the
XRT8001 could be configured to operate in this “Factory-Test” Mode. Since all “Factory-Test” Mode registers are reset to “0”, upon
chip power, this should not be a problem for the user.
However, if the user performs write operations to “non-defined” address locations within the XRT8001, then the user may observe strange
operation from the XRT8001. The user must make sure that when the Microcontroller performs WRITE operations to the XRT8001, it
is only performing these WRITE operations to the Address Locations defined in the XRT8001 Data Sheet.
Rev. 1.01
5
5 Page 
XRT8001
2.2 The Reverse/Master Mode
In the Reverse/Master Mode, the XRT8001 will accept
either a 56kHz or a 64kHz clock signal via the FIN input
pin, and will generate either a 1.544MHz or a 2.048MHz
clock signal via the Clock Output signals.
Figure 8, presents a simple illustration of the XRT8001
WAN Clock operating in the “Reverse/Master Mode.”
56kHz
or
64kHz
FIN CLK1
XXRRTT88000011
WWAANN CClloocckk
CLK2
1.544MHz
or
2.048MHz
1.544MHz
or
2.048MHz
Figure 8. Illustration of the XRT8001 WAN Clock
Operating in the Reverse/Master Mode
Rev. 1.01
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT8001.PDF ] | |
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