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PDF XRT72L13 Data sheet ( Hoja de datos )

Número de pieza XRT72L13
Descripción M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
Fabricantes ETC 
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PRELIMINARY
XRT72L13
APRIL 2001
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
GENERAL DESCRIPTION
The XRT72L13 is a fully integrated, low power, Multi-
plexer/Framer IC which performs Multiplexing/De-
mutiplexing of 28 DS1or 21 E1 signals into/from a
DS3 signal with either M13 or C-bit parity frame for-
mat, performs Clear Channel DS3 Framing, and sup-
ports High speed HDLC/LAPD data linking.
The XRT72L13 also contains M12 and M23 bit-inter-
leaving multiplexing/demultiplexing functions with
necessary stuffing and destuffing control. Seven in-
ternal DS2/G.747 framers are included to support
Mux/Demux purposes.
The XRT72L13 contains an integral DS3 Framer
which provides Clear Channel DS3 Framing and Er-
ror Accumulation in accordance with ANSI/ITU-T
specifications.
The XRT72L13 provides the intelligent functions of
DS3/DS2 mode control, signaling control, error and
alarm reporting and handles the HDLC/LAPD data
link through internal registers accessible via an 8-bit
parallel, memory mapped, µProcessor interface.
FEATURES
A fully integrated device that supports:
Multiplexing/Demultiplexing Mode
Clear Channel DS3 Framer Mode
High Speed HDLC Controller Mode
Supports Multiple Loop-back modes
Smooths gapped clock signals
Supports Intel or Motorola PIO µP interfaces
Available in a 208 pin PQFP package
Single 3.3V Power Supply
5V Tolerant I/O
Operates over the Industrial Temperature Range
APPLICATIONS
M13 Multiplexer/Demuliplexer Applications.
Frame Relay Systems
Digital Access and Cross Connect Systems
Local Digital Switch
Add/Drop Multiplexers
DS3 Data/Channel Service Units.
Test Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT72L13 MULTIPLEXER/FRAMER
TxHDLC
ConTxtrHoDlleLrC
Controller
TxHDLC[0:7]
TxHDLCClk
Send_FCS
TxPOS
TxNEG
TxLine Clk
RxPOS
RxNEG
RxLine Clk
Clear Channel
DCSle3aFr rCamhaenr nel
DS3 Framer
32/64 Bit
De-Jitter
FIFO
M23
MUMX23
MUX
M12
MUMX12
MUX
DS2 or G.747
Data Streams
M23
DEMMU2X3
DEMUX
M12
DEMUX
TxDS1[0:27]
TxClk[0:27]
RxDS1[0:27]
RxClk[0:27]
Microprocessor
MIinctreorpfarocceessor
Interface
RxHDLC
CoRntxrHoDlleLrC
Controller
RxHdlc[0:7]
RxHDLCClk
RxIdle
Valid-FCS
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XRT72L13 pdf
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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................... 84
PART NUMBER REGISTER (ADDRESS = 0X02) ............................................................................................. 85
VERSION NUMBER REGISTER (ADDRESS = 0X03) ........................................................................................ 85
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................................... 86
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) ......................................................................... 86
RXFIFO CONTROL REGISTER (ADDRESS = 0X06) ........................................................................................ 87
M23 CONFIGURATION REGISTER (ADDRESS = 0X07) ................................................................................. 87
TABLE 5: ................................................................................................................................................. 89
M23 TX DS2 AIS REGISTER (ADDRESS = 0X08) ....................................................................................... 89
M23 REQUEST LOOPBACK REGISTER (ADDRESS = 0X09) ........................................................................... 90
M23 LOOPBACK ACTIVATION REGISTER (ADDRESS = 0X0A) ....................................................................... 90
M23 RX DS2 AIS REGISTER (ADDRESS = 0X0B) ...................................................................................... 90
DS3 TEST REGISTER (ADDRESS = 0X0C) .................................................................................................. 91
RX DS3 CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X10) ........................................................... 92
RX DS3 STATUS REGISTER (ADDRESS = 0X11) ........................................................................................... 93
RX DS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ......................................................................... 94
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ........................................................................ 95
RX DS3 SYNC DETECT REGISTER (ADDRESS = 0X14) ................................................................................. 96
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) .................................................. 97
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) .............................................................................. 97
RXDS3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 98
M12 DS2 # 1 CONFIGURATION REGISTER (ADDRESS = 0X1A) .................................................................... 99
M12 DS2 # 2 CONFIGURATION REGISTER (ADDRESS = 0X1B) .................................................................. 100
M12 DS2 # 3 CONFIGURATION REGISTER (ADDRESS = 0X1C) .................................................................. 100
M12 DS2 # 4 CONFIGURATION REGISTER (ADDRESS = 0X1D) .................................................................. 101
M12 DS2 # 5 CONFIGURATION REGISTER (ADDRESS = 0X1E) .................................................................. 102
M12 DS2 # 6 CONFIGURATION REGISTER (ADDRESS = 0X1F) .................................................................. 103
M12 DS2 # 7 CONFIGURATION REGISTER (ADDRESS = 0X20) .................................................................. 104
M12 DS2 # 1 AIS REGISTER (ADDRESS = 0X21) ...................................................................................... 105
M12 DS2 # 2 AIS REGISTER (ADDRESS = 0X22) ...................................................................................... 106
M12 DS2 # 3 AIS REGISTER (ADDRESS = 0X23) ...................................................................................... 107
M12 DS2 # 4 AIS REGISTER (ADDRESS = 0X24) ...................................................................................... 108
M12 DS2 # 5 AIS REGISTER (ADDRESS = 0X25) ...................................................................................... 109
M12 DS2 # 6 AIS REGISTER (ADDRESS = 0X26) ...................................................................................... 110
M12 DS2 # 7 AIS REGISTER (ADDRESS = 0X27) ...................................................................................... 111
M12 DS2 # 1 LOOP-BACK REGISTER (ADDRESS = 0X28) ......................................................................... 112
M12 DS2 # 2 LOOP-BACK REGISTER (ADDRESS = 0X29) ......................................................................... 113
M12 DS2 # 3 LOOP-BACK REGISTER (ADDRESS = 0X2A) ........................................................................ 114
M12 DS2 # 4 LOOP-BACK REGISTER (ADDRESS = 0X2B) ........................................................................ 116
M12 DS2 # 5 LOOP-BACK REGISTER (ADDRESS = 0X2C) ........................................................................ 117
M12 DS2 # 6 LOOP-BACK REGISTER (ADDRESS = 0X2D) ........................................................................ 118
M12 DS2 # 7 LOOP-BACK REGISTER (ADDRESS = 0X28) ......................................................................... 119
TX DS3 CONFIGURATION REGISTER (ADDRESS = 0X30) ........................................................................... 120
TRANSMIT DS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) ................................................ 121
TX DS3 FEAC REGISER (ADDRESS = 0X32) ............................................................................................ 122
TXDS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) .................................................................. 122
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 123
TXDS3 M-BIT MASK REGISTER (ADDRESS = 0X35) .................................................................................. 124
TX DS3 F-BIT MASK REGISTER - 1 (ADDRESS = 0X36) ............................................................................. 124
TXDS3 F-BIT MASK REGISTER - 2 (ADDRESS = 0X37) .............................................................................. 125
TX DS3 F-BIT MASK REGISTER - 3 (ADDRESS = 0X38) ............................................................................. 125
TXDS3 F-BIT MASK REGISTER - 4 (ADDRESS = 0X39) .............................................................................. 125
DS2 # 1 FRAMER CONFIGURATION REGISTER (ADDRESS = 0X3A) ............................................................ 126
DS2 # 2 FRAMER CONFIGURATION REGISTER (ADDRESS = 0X3B) ............................................................ 127
III

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XRT72L13 arduino
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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
FIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ............ 274
TABLE 25: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (TX LOS) WITHIN THE TX DS3 CONFIGURA-
TION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ....................... 274
TX DS3 M-BIT MASK REGISTER, ADDRESS = 0X35 .................................................................................. 275
TX DS3 F-BIT MASK1 REGISTER, ADDRESS = 0X36 ................................................................................. 275
TX DS3 F-BIT MASK2 REGISTER, ADDRESS = 0X37 ................................................................................. 276
TX DS3 F-BIT MASK3 REGISTER, ADDRESS = 0X38 ................................................................................. 276
TX DS3 F-BIT MASK4 REGISTER, ADDRESS = 0X39 ................................................................................. 276
4.2.5 The Transmit DS3 Line Interface Block ............................................................................................. 276
Figure 84. Approach to Interfacing the XRT72L13 Framer IC device to the XRT7300 DS3/E3/STS-1
Transmitter LIU .................................................................................................................... 277
Figure 85. A Simple Illustration of the "Transmit DS3 LIU Interface" block .................................. 278
Figure 86. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit
DS3 LIU Interface is operating in the Unipolar Mode ....................................................... 278
I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................. 279
TABLE 26: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O
CONTROL REGISTER AND THE TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE ........... 279
Figure 87. Illustration of AMI Line Code ........................................................................................... 280
Figure 88. Illustration of two examples of B3ZS Encoding ............................................................. 280
I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................. 281
TABLE 27: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE "I/O CONTROL" REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK ............... 281
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................ 281
TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE "I/O CONTROL"
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ....... 281
Figure 89. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and Tx-
NEG are configured to be updated on the rising edge of TxLineClk ............................. 282
Figure 90. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and Tx-
NEG are configured to be updated on the falling edge of TxLineClk ............................. 282
4.2.6 Transmit Section Interrupt Processing ............................................................................................... 282
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ........................................................................ 283
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) ..................................... 283
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) ..................................... 284
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 284
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 285
4.3 THE RECEIVE SECTION OF THE XRT72L13 (DS3 MODE OPERATION) .............................................................. 285
Figure 91. A Simple Illustration of the Receive Section of the XRT72L13, when it has been config-
ured to operate in the DS3 Mode ....................................................................................... 286
4.3.1 The Receive DS3 LIU Interface Block ............................................................................................... 286
Figure 92. A Simple Illustration of the "Receive DS3 LIU Interface" Block ................................... 287
Figure 93. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar
Data ...................................................................................................................................... 288
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................ 288
TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE "I/O CONTROL"
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ....... 288
Figure 94. Illustration on how the Receive DS3 Framer (within the XRT72L13 Framer IC) being inter-
face to theXRT7300 Line Interface Unit, while the Framer is operating in Bipolar Mode ....
289
Figure 95. Illustration of AMI Line Code ........................................................................................... 289
Figure 96. Illustration of two examples of B3ZS Decoding ............................................................. 290
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................ 291
TABLE 30: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REG-
ISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL .................................................... 291
Figure 97. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS
and RxNEG are to be sampled on the rising edge of RxLineClk .................................... 291
IX

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