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PDF XR17L152IM Data sheet ( Hoja de datos )
| Número de pieza | XR17L152IM | |
| Descripción | 3.3V PCI BUS DUAL UART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR17L152
3.3V PCI BUS DUAL UART
AUGUST 2003
REV. 1.1.0
GENERAL DESCRIPTION
The XR17L1521 (L152) is a monolithic dual PCI Bus
Universal Asynchronous Receiver and Transmitter (UART)
in Exar’s PCI Bus UART family. The device is designed to
meet today’s 32-bit PCI Bus and high bandwidth
requirements in communication systems. The global
interrupt source register provides a complete interrupt
status indication for both channels to speed up interrupt
parsing. Each UART is independently controlled and has its
own 16C550 compatible 5G (Fifth Generation) register set,
transmit and receive FIFOs of 64 bytes, fully programmable
transmit and receive FIFO trigger levels, transmit and
receive FIFO level counters, automatic hardware flow
control with programmable hysteresis, automatic software
(Xon/Xoff) flow control, automatic half-duplex control
output, wireless IrDA (Infrared Data Association) infrared
encoder/decoder, 8 multi-purpose definable inputs/outputs,
and a 16-bit general purpose timer/counter.
NOTE: 1 Covered by U.S. Patents #5,649,122, #5,949,787
APPLICATIONS
• Network Management
• Factory Automation and Process Control
• Ethernet Network to Serial Ports
• Point-of-Sale Systems
• Multi serial ports RS-232/RS-422/RS-485 Cards
FEATURES
• High Performance DUART
• PCI Bus 2.2 Target Interface Compliance
• 3.3 V PCI Bus Compliant up to 33 MHz Clock
• 5 Volt Tolerant Serial Inputs
• 32-bit PCI Bus Interface with EEPROM Interface
• A Global Interrupt Source Register for both UARTs
• Data Transfer in Byte, Word and Double-word
• Data Read/Write Burst Operation
• Each UART is independently controlled with:
•16C550 Compatible 5G Register Set
•64-byte Transmit and Receive FIFOs
•Transmit and Receive FIFO Level Counters
•Programmable TX and RX FIFO Trigger Level
•Automatic RTS/CTS or DTR/DSR Flow Control
•Automatic Xon/Xoff Software Flow Control
•Automatic RS485 Half-duplex Control Output with
Selectable Turn-around Delay (0 to 15 bit-times)
•Infrared (IrDA 1.0) Data Encoder/Decoder
•Programmable Data Rate with Prescaler
•Up to 3.125 Mbps Data Rate at 8X Sampling
• Eight Multi-Purpose Inputs/outputs
• A General Purpose 16-bit Timer/Counter
• Sleep Mode with Automatic Wake-up Indicator
• Same package and pin-out as XR17C152 and
XR17D152 (14x14x1.0 mm TQFP)
FIGURE 1. BLOCK DIAGRAM
CLK
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
INTA#
IDSEL
PERR#
SERR#
PAR
EECK
EEDI
EEDO
EECS
ENIR
EN485#
PCI Local
Bus
Interface
Device
Configuration
Registers
Configuration
Space
Registers
EEPROM
Interface
16-bit
Timer/Counter
*5V Tolerance for non-PCI Inputs
UART Channel 0
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel 1
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
Multi-pur.pose
Inputs/Outputs
Crystal Osc/Buffer
3.3V VCC
GND
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
TX1, RX1, DTR1#,
DSR1#, RTS1#,
CTS1#, CD1#, RI1#
MPIO0- MPIO7
XTAL1
XTAL2
TMRCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
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PIN DESCRIPTIONS
NAME
XTAL1
PIN #
77
TYPE
DESCRIPTION
I Crystal or external clock input of up to data rate of 3.125Mbps at 33MHz 3.3V
and 8X sampling. See AC Characterization table. Caution: this input is not 5V
tolerant.
XTAL2
76 O Crystal or buffered clock output.
TMRCK
75 I 16-bit timer/counter external clock input.
ENIR
74 I Global Infrared mode enable (active high). During power up or reset, this pin
is sampled and if it is a logic high, both UARTs are set for infrared mode. Also,
the infrared mode bit, MCR[6], is set in both channels. Software can override
this pin thereafter and enable or disable infrared mode.
EN485#
65 I Global AutoRS485 half-duplex direction control enable (active low). During
power up or reset, this pin is sampled and if it is a logic high, both UARTs are
set for Auto RS485 Mode. Also, the Auto RS485 bit, FCTR[5], is set in both
channels. Software can override this pin thereafter and enable or disable it.
TEST#
VCC
79
54, 80
I Factory Test. Connect to VCC for normal operation.
PWR 5V or 3.3V power supply for the core logic.
VI/O
10, 22, 32, 43, PWR PCI bus I/O power supply. 3.3V ONLY (PCI 2.2 Compliance).
89, 100
GND
1, 11, 23, 33, PWR Power supply common, ground.
44, 53, 78, 88
NC 63, 64
No Connection.
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
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XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
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TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS
[A7:A0]
REGISTER
READ/WRITE COMMENT
RESET STATE
Ox091
Ox092
MPIO3T
MPIOINV
Read/Write MPIO output control
Read/Write MPIO input polarity select
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Ox093
MPIOSEL Read/Write MPIO select
Bits 7-0 = 0xFF
TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT
ADDRESS
0x080-083
0x084-087
0x088-08B
0x08C-08F
0x090-093
REGISTER
INTERRUPT (read-only)
TIMER (read/write)
ANCILLARY1 (read/write)
ANCILLARY2 (read-only)
MPIO (read/write)
BYTE 3 [31:24] BYTE 2 [23:16]
INT3
INT2
TIMERMSB
TIMERLSB
SLEEP
RESET
MPIOINT
MPIOSEL
REGB
MPIOINV
BYTE 1 [15:8]
INT1
TIMER
(reserved)
REGA
(reserved)
DVID
MPIO3T
BYTE 0 [7:0]
INT0
TIMERCNTL
8XMODE
DREV
MPIOLVL
1.2.1 The Interrupt Status Register
The XR17L152 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is a 2-bit indicator in INT0 register representing the 2
channels with the first 3 bits representing each channel from 0 to 1. This permits the interrupt routine to quickly
vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0
represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port
status requires service. INT0 bit-1 provides interrupt status for channel 1 and bits 2 to 7 are reserved and
remain at a logic 0.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code per channel. This 3-bit code represents 7 interrupts corresponding to individual
UART’s transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 6-bit interrupt
status for both channels. Bits 8, 9 and 10 represents channel 0 and bits 11,12 and 13 represents channel 1.
Bits 14 to 31 are reserved and remain at logic zero. Both channels interrupt status are available with a single
DWORD read operation. This feature allows the host to quickly vector and serve the interrupts, reducing
service interval, hence, reducing host bandwidth requirements.
GLOBAL INTERRUPT REGISTER (DWORD) [default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
Upon power-up or reset, all bits are a logic 0. A special interrupt condition is generated by the L152 upon
awakening from sleep after both channels were put to sleep mode earlier. Figure 4 shows the 4-byte interrupt
register and its make up.
INT0 [7:0] Channel Interrupt Indicator.
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-1
indicates channel 1. Logic one indicates the channel N [1:0] has requested for service. Bits 2 to 7 are reserved
and remain at logic zero The interrupt bit clears after reading the appropriate register of the interrupting
channel register, see Interrupt Clearing section.
11
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