PDF XR16L784 Data sheet ( Hoja de datos )

Número de pieza	XR16L784
Descripción	HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
Fabricantes	Exar Corporation
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No Preview Available ! áç XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART JUNE 2004 GENERAL DESCRIPTION FEATURES REV. 1.2.0 The XR16L7841 (784) is a quad Universal Asynchronous Receiver and Transmitter (UART). The device is designed for high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 4 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, transmit and receive FIFOs of 64 bytes, fully programmable transmit and receive FIFO level triggers, transmit and receive FIFO level counters, automatic RTS/CTS or DTR/ DSR hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, IrDA (Infrared Data Association) encoder/ decoder, and a 16-bit general purpose timer/counter. NOTE: 1 Covered by U.S. Patents #5,649,122 and #5,949,787 APPLICATIONS • Remote Access Servers • Ethernet Network to Serial Ports • Network Management • Factory Automation and Process Control • Point-of-Sale Systems • Multi-port RS-232/RS-422/RS-485 Cards • 2.97V to 5.5V operation with 5V Tolerant Inputs • 8-bit Intel or Motorola Data Bus Interface • Single Open Drain Interrupt output for all 4 channels • Global Interrupt Source Registers for all channels • 5G (Fifth Generation) “Flat” Register Set • Each UART is Independently Controlled with: •16C550 Compatible Registers •64-byte Transmit and Receive FIFOs •Transmit and Receive FIFO Level Counters •Programmable TX and RX FIFO Trigger Levels •Automatic RTS/CTS or DTR/DSR Flow Control •Selectable RTS Flow Control Hysteresis •Automatic Xon/Xoff Software Flow Control •Automatic RS485 Half-duplex Control Output with 16 Selectable Turn-around Delay •Infrared (IrDA 1.1) Data Encoder/Decoder •Programmable Data Rate with Prescaler •Up to 3.12 (16x) and 6.25 (8x) Mbps Data Rate • A General Purpose 16-bit Timer/Counter • Sleep Mode with Automatic Wake-up Indicator • 64-pin TQFP Package (10x10x1.4 mm) FIGURE 1. BLOCK DIAGRAM A7:A0 D7:D0 IOR# IOW# CS# INT# 16/68# RST# ENIR Intel or Motorola Data Bus Interface Device Configuration Register s 16-bit Timer/Counter *All Inputs are 5V Tolerant (Except XTAL1) UART Channel 0 UART Regs BRG 64 Byte TX FIFO TX & RX IR ENDEC 64 Byte RX FIFO UART Channel 1 UART Channel 2 UART Channel 3 Crystal Osc/ Buffer 2.97V to 5.5V VCC GND TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# TX3, RX3, DTR3#, DSR3#, RTS3#, CTS3#, CD3#, RI3# XTAL1 XTAL2 TMRCK 784BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page áç REV. 1.2.0 Pin Descriptions NAME PIN # TX3 28 RX3 21 RTS3# 26 CTS3# 22 DTR3# 27 DSR3# 23 CD3# 24 RI3# 25 ANCILLARY SIGNALS XTAL1 50 XTAL2 49 TMRCK 31 ENIR 32 RST# 16/68# VCC GND 20 19 9,30,52 10,29,51 XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART TYPE DESCRIPTION O UART channel 3 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. I UART channel 3 Receive Data or infrared receive data. Normal RXD input idles HIGH while infrared RXD input idles LOW. In the infrared mode, the polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a logic 1, a HIGH on the RXD input is considered a space. O UART channel 3 Request to Send or general purpose output (active low). See description of RTS0# pin. I UART channel 3 Clear to Send or general purpose input (active low).d. See description of CTS0# pin. O UART channel 3 Data Terminal Ready or general purpose output (active low). See description of DTS0# pin. I UART channel 3 Data Set Ready or general purpose input (active low). See description of DSR0# pin. I UART channel 3 Carrier Detect or general purpose input (active low). I UART channel 3 Ring Indicator or general purpose input (active low). I Crystal or external clock input. Caution: this input is not 5V tolerant. O Crystal or buffered clock output. I 16-bit timer/counter external clock input. I Infrared mode enable (active high). This pin is sampled during power up, fol- lowing a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up all 8 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART. I Reset (active low). The configuration and UART registers are reset to default values, see Table-15. I Intel or Motorola data bus interface select. HIGH selects Intel bus interface and LOW selects Motorola interface. This input affects the functionality of IOR#, IOW# and CS# pins. +5V or +3.3V supply, all inputs are 5V tolerant except for XTAL1. Power supply common, ground. NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. 5 5 Page áç REV. 1.2.0 XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 2.8.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE 16X or 8X Clock Receive Data Shift Register (RSR) Data Bit Validation Receive Data Characters Receive Data Byte and Errors Error Tags in LSR bits 4:2 Receive Data Holding Register (RHR) RHR Interrupt (ISR bit-2) RXFIFO1 FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE 16X or 8X Clock 64 bytes by 11-bit wide FIFO Receive Data Byte and Errors Receive Data Shift Register (RSR) Receive Data FIFO Receive Data Data Bit Validation Receive Data Characters Example: - RX FIFO trigger level selected at 16 bytes (See Note Below) Data falls to 8 RTS# re-asserts when data falls below the flow control trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-2. FIFO Trigger=16 RHR Interrupt (ISR bit-2) programmed for desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 Data fills to 24 RTS# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-2. RXFIFO1 NOTE: Table-B selected as Trigger Table for Figure 9 (Table 14 on page 31). 11 11 Page

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