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PDF XR16L2751 Data sheet ( Hoja de datos )
| Número de pieza | XR16L2751 | |
| Descripción | 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
SEPTEMBER 2002
REV. 1.0.0
GENERAL DESCRIPTION
The XR16L27511 (2751) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
includes 2 additional capabilities over the
XR16L2750: Intel and Motorola data bus selection
and a “PowerSave” mode to further reduce sleep
current to a minimum during sleep mode. The 2751’s
register set is compatible to the ST16C2550 and
XR16C2850 but with added functions. It supports the
Exar’s enhanced features of 64 bytes of TX and RX
FIFOs, programmable FIFO trigger level, FIFO level
counters, automatic hardware and software flow
control, automatic RS-485 half duplex direction
control with programmable turn-around delay, and a
complete modem interface. Onboard registers
provide the user with operational status and data
error tags. An internal loopback capability allows
onboard diagnostics. Independent programmable
baud rate generator is provided in each UART
channel to support data rates up to 6.25 Mbps.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205
APPLICATIONS
• Portable and Battery Operated Appliances
• Wireless Access Servers
• Ethernet Network Routers
• Cellular Data Devices
• Telecommunication Network Routers
• Factory Automation and Process Controls
FIGURE 1. XR16L2751 BLOCK DIAGRAM
FEATURES
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Functionally Compatible to ST16C2550
XR16C2850 with 4 additional inputs
• Intel or Motorola Data Bus Interface Select
• Two Independent UARTs
and
s Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt,
and 3 Mbps at 2.5 Volt with 8X sampling rate
s 64 bytes of Transmit and Receive FIFOs
s Transmit and Receive FIFO Level Counters
s Programmable TX and RX FIFO Trigger Levels
s Automatic Hardware (RTS/CTS) Flow Control
s Selectable RTS Flow Control Hysteresis.
s Automatic Software (Xoff/Xon) Flow Control
s Automatic RS-485 2-wire Half-duplex Direction
Control to the Transceiver via RTS#
s Full Modem Interface
s Infrared Receive and Transmit Encoder/
decoder
• PowerSave Feature reduces sleep current to 15 µA
at 3.3 Volt
• Device Identification
• Crystal or external clock input
• Industrial and Commercial Temperature ranges
• 48 TQFP Package (7 x 7 x 1.0 mm)
PwrSave
A2:A0
D7:D0
IOR# (VCC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (logic 0)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset (Reset#)
16/68#
CLKSEL
HDCNTL#
Intel or
Motorola
Data Bus
Interface
*5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
64 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 5.5 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
2751BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
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Pin Description
NAME
RXB
RTSB#
CTSB#
DTRB#
DSRB#
CDB#
RIB#
OP2B#
48-TQFP
PIN #
4
22
23
35
20
16
21
9
TYPE
DESCRIPTION
I UART channel B Receive Data or infrared receive data. Normal receive data input
must idle at logic 1 condition. The infrared receiver pulses typically idles at logic 0 but
can be inverted by software control prior going in to the decoder, see MCR[6] and
FCTR[2].
O UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
I UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
O UART channel B Data-Terminal-Ready (active low) or general purpose output.
I UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
I UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
I UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
O Output Port 2 Channel B - The output state is defined by the user and through the
software setting of MCR[3]. When MCR[3] is set to a logic 1, INTB is set to the level
mode and OP2B# output to a logic 0. When MCR[3] is set to a logic 0, INTB is set to
the three state mode and OP2B# to a logic 1. See MCR[3]. This output must not be
used as a general output when the interrupt output is used else it will disturb the
INTB output functionality.
ANCILLARY SIGNALS
XTAL1
13
XTAL2
14
PwrSave
12
16/68#
24
CLKSEL
25
I Crystal or external clock input. This input is not 5V tolerant.
O Crystal or buffered clock output. This output may be use to drive a clock buffer which
can drive other device(s).
I PowerSave (active high). This feature isolates the 2751’s data bus interface from the
host preventing other bus activities that cause higher power drain during sleep mode.
See Sleep Mode with Auto Wake-up and PowerSave Feature section for details.
I Intel or Motorola Bus Select.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate in the Intel bus
type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will operate in the
Motorola bus type of interface.
I Baud-Rate-Generator Input Clock Prescaler Select for channel A and B. This input is
only sampled during power up or a reset. Connect to VCC for divide by 1 (default)
and GND for divide by 4. MCR[7] can override the state of this pin following a reset or
initialization. See MCR bit-7 and Figure 6 in the Baud Rate Generator section.
5
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XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
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2.9 Crystal Oscillator or External Clock Input
The 2751 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum voltage at the pin should be VCC. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
C1
22-47pF
XTAL2
R2
500K - 1M
R1
0-120
(Optional)
Y1
1.8432 MHz
to
24 MHz
C2
22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 5). The programmable Baud
Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an
external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as shown in Figure 5) it can
extend its operation up to 50 MHz (6.25 Mbps serial data rate) at 5V with an 8X sampling rate.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
E xte rn a l C lo ck
vcc
gnd
VCC
R1
2K
XTAL1
XTAL2
For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at
http://www.exar.com.
2.10 Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by CLKSEL
hardware pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input
crystal or external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the
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| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet XR16L2751.PDF ] | |
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