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PDF XR16C850 Data sheet ( Hoja de datos )
| Número de pieza | XR16C850 | |
| Descripción | UART with 128-byte FIFOs FIFO Counters and Half-duplex Control | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR16C850
UART with 128-byte FIFO’s
FIFO Counters and Half-duplex Control
GENERAL DESCRIPTION
The XR16C850*1 (850) is a universal asynchronous
receiver and transmitter (UART) and is pin compatible
with the ST16C550,ST16C650A, and TI’s TL16C750
UART. The 850 is an enhanced UART with 128 byte
FIFOs, automatic hardware/software flow control, and
data rates up to 1.5Mbps. It includes transmit/receive
FIFO counters to increase data loading and unloading
throughput. Onboard status registers provide error indi-
cations and operational status. Modem interface con-
trol is included and can be optionally configured to
operate with the Infrared (IrDA) encoder/decoder. Inter-
nal loopback allows onboard diagnostics. The 850 is
available in 40-pin PDIP, 44-pin PLCC, 48-pin TQFP,
and 52-pin QFP packages. The 44, 48, and 52 pin
versions provide both the standard (STD) mode or PC
mode. The STD mode is compatible with the ST16C450,
ST16C550, ST16C650A and TL16C750 while the PC
mode supports standard PC COM port connections.
The 40 PDIP pin package does not offer the PC mode.
D5
D6
D7
RCLK
RX
N.C.
TX
CS0
CS1
-CS2
-BAUDOUT
7
8
9
10
11
12
13
14
15
16
17
PLCC Package
June 1999-1
XR16C850CJ
"STD" MODE
CONNECTION
39 RESET
38 -OP1
37 -DTR
36 -RTS
35 -OP2
34 N.C.
33 INT
32 -RXRDY
31 A0
30 A1
29 A2
FEATURES
• Pin to pin compatible to ST16C550, ST16C650A and
TL16C750
• Transmit/receive FIFO counters
• 128 bytes of Transmit/Receive FIFO
• RS-485 half duplex direction control
• Automatic software/hardware flow control
• Programmable, selectable transmit/receive trigger
levels
• Infrared transmitter and receiver encoder/decoder
• Up to 1.5Mbps data rate
• Sleep mode (100µA standby)
• Small 7x7mm TQFP
• +5 or 3.3 Volts operation
• Windows2 drivers available
D5
D6
D7
S2
RX
A4
TX
A5
A6
A7
-LPT1
7
8
9
10
11
12
13
14
15
16
17
XR16C850CJ
"PC" MODE
CONNECTION
39 RESET
38 -OP1
37 -DTR
36 -RTS
35 S3
34 GND
33 IRQA
32 IRQB
31 A0
30 A1
29 A2
ORDERING INFORMATION
Part Number Pins Package Operating Temperature
XR16C850CP 40 PDIP
0° C to + 70° C
XR16C850CJ 44 PLCC
0° C to + 70° C
XR16C850CM 48 TQFP
0° C to + 70° C
XR16C850CQ 52 QFP
0° C to + 70° C
Note *1: Covered by U.S. patent # 5,649,122 and patent pending.
Note *2: Windows is a trademark of Microsoft Corporation.
Part Number
XR16C850IP
XR16C850IJ
XR16C850IM
XR16C850IQ
Pins
40
44
48
52
Package Operating Temperature
PDIP
-40° C to + 85° C
PLCC
-40° C to + 85° C
TQFP
-40° C to + 85° C
QFP
-40° C to + 85° C
Rev. 1.20
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
1 page  
XR16C850
SYMBOL DESCRIPTION
Symbol
A0
A1
A2
A3 / IOR
A4
A5 / CS0
A6 / CS1
A7 / -CS2
Pin Signal
40 44 48 52 type
Pin Description
28 31 28 31
I Address-0 Select Bit - Internal registers address
selection in PC and STD modes.
27 30 27 30
I Address-1 Select Bit Internal registers address
selection in PC and STD modes
26 29 26 29
I Address-2 Select Bit Internal registers address
selection in PC and STD modes
22 25 20 22
I Address-3 Select Bit or Input/Output Read (dual
function) - When the PC mode is selected, this pin
is used as 4th address line to decode the COM1-4
and LPT ports. During STD mode operation this pin
is used as Read strobe. Its function is the same as
-IOR (see -IOR), except it is active high. Either an
active -IOR or IOR is required to transfer data from
850 to CPU during a read operation. Connect this
pin to GND when –IOR is used.
- 12 6 6 I Address-4 Select Bit (internal pull-up) - When the
PC mode is selected, this pin is used as 5th address
line to decode the COM1-4 and LPT ports. This pin
has no function in the STD mode.
12 14
9
9
I Address-5 Select Bit or Chip Select-0 (dual function)
- When the PC mode is selected, this pin is used as
6th address line to decode the COM1-4 and LPT
ports. During STD mode a logical 1 on this pin
provides the chip select 0 function. Connect this pin
to VCC when CS1 or –CS2 is used.
13 15 10 10
I Address-6 Select Bit or Chip Select-1 (dual function)
- When the PC mode is selected, this pin is used as
7th address line to decode the COM1-4 and LPT
ports. During STD mode a logical 1 on this pin
provides the chip select 1 function. Connect this pin
to VCC when CS0 or –CS2 is used.
14 16 11
7
I Address-7 Select Bit or Chip Select -2 (dual func-
tion) - When the PC mode is selected, this pin is
used as 8th address line to decode the COM1-4 and
LPT ports. During STD mode a logical 1 on this pin
provides the chip select 2 function. Connect this pin
Rev. 1.20
5
5 Page 
XR16C850
SYMBOL DESCRIPTION
Symbol
-DSR
-DTR
-RI
-RTS
RX / IRRX
Pin Signal
40 44 48 52 type
Pin Description
reading MSR bit-4. This pin only affects the transmit
and receive operations when Auto CTS function is
enabled via the Enhanced Feature Register (EFR)
bit-7, for hardware flow control operation.
37 41 39 42
I Data Set Ready (active low) - A logic 0 on this pin
indicates the modem or data set is powered-on and
is ready for data exchange with the UART. This pin
has no effect on the UART’s transmit or receive
operation.
33 37 33 36 O Data Terminal Ready (active low) - A logic 0 on this
pin indicates that the 850 is powered-on and ready.
This pin can be controlled via the modem control
register. Writing a logic 1 to MCR bit-0 will set the -
DTR output to logic 0, enabling the modem. This pin
will be a logic 1 after writing a logic 0 to MCR bit-0,
or after a reset. This pin has no effect on the UART’s
transmit or receive operation.
39 43
41 44
I Ring Indicator (active low) - A logic 0 on this pin
indicates the modem has received a ringing signal
from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
32 36 32 35 O Request to Send (active low) - A logic 0 on the -RTS
pin indicates the transmitter has data ready and
waiting to send. Writing a logic 1 in the modem
control register (MCR bit-1) will set this pin to a logic
0 indicating data is available. After a reset this pin
will be set to a logic 1. This pin only affects the
transmit and receive operations when Auto RTS
function is enabled via the Enhanced Feature Reg-
ister (EFR) bit-6, for hardware flow control operation.
10 11
7
7
I Receive Data - This pin provides the serial receive
data input to the 850. Two user selectable interface
options are available. The first option supports the
standard serial interface. The second option pro-
vides an Infrared decoder interface, see figures 2 and
3. When using the standard modem interface, the
RX input must be a logic 1 during idle (no data
Rev. 1.20
11
11 Page | ||
| Páginas | Total 55 Páginas | |
| PDF Descargar | [ Datasheet XR16C850.PDF ] | |
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