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PDF XQ18V04VQ44N Data sheet ( Hoja de datos )

Número de pieza XQ18V04VQ44N
Descripción QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
Fabricantes Xilinx 
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0
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DS082 (v1.2) November 5, 2001
05
Features
• In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
- Endurance of 2,000 program/erase cycles
- Program/erase over full military temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Cascadable for storing longer or multiple bitstreams
• Dual configuration modes
- Serial Slow/Fast configuration (up to 33 MHz)
- Parallel (up to 264 Mbps at 33 MHz)
• Low-power advanced CMOS FLASH process
• 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals.
• 3.3V or 2.5V output capability
• Available in CC44 and VQ44 packages.
• Design support using the Xilinx Alliance™ and
Foundation™ series software packages.
• JTAG command initiation of standard FPGA
configuration.
• Available to Standard Microcircuit Drawing
5962-01525.
- For more information contact Defense Supply
Center Columbus (DSCC) at
http://www.dscc.dla.mil
CLK CE
QPro XQ18V04 (XQR18V04) QML
In-System Programmable
Configuration PROMs
Preliminary Product Specification
Radiation Hardenned XQR18V04
• Fabricated on Epitaxial Substrate
• Latch-Up Immune to >120 LET
• Guaranteed TID of 40 kRad(Si)
• Supports SEU Scrubbing
Description
Xilinx introduces the QPro™ XQ18V04 and XQR18V04
series of QML in-system programmable and radiation hard-
ened configuration PROMs. Initial devices in this 3.3V fam-
ily are a 4-megabit PROM that provide an easy-to-use,
cost-effective method for re-programming and storing large
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROMs DATA (D0-D7) pins.
The data will be clocked into the FPGA on the following ris-
ing edge of the CCLK. Neither Express nor SelectMAP uti-
lize a Length Count, so a free-running oscillator may be
used. See Figure 6.
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CEO
D0 DATA
(Serial or Parallel
[Express/SelectMAP] Mode)
7
D[1:7]
Express Mode and
SelectMAP Interface
CF
Figure 1: XQ18V04 Series Block Diagram
DS026_01_021000
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS082 (v1.2) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1

1 page




XQ18V04VQ44N pdf
R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
V CC
GND
(a)
(b)
DS026_02_011100
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
IEEE 1149.1 Boundary-Scan (JTAG)
The XQ(R)18V04 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addi-
tion, the JTAG interface is used to implement in-system pro-
gramming (ISP) to facilitate configuration, erasure, and
verification operations on the XQ(R)18V04 device.
Table 3 lists the required and optional boundary-scan
instructions supported in the XQ(R)18V04. Refer to the
IEEE Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
Table 3: Boundary Scan Instructions
Boundary-Scan Binary
Command Code [7:0]
Description
Required Instructions
BYPASS
11111111 Enables BYPASS
SAMPLE/
PRELOAD
00000001
Enables boundary-scan
SAMPLE/PRELOAD
operation
EXTEST
00000000 Enables boundary-scan
EXTEST operation
Optional Instructions
CLAMP
11111010 Enables boundary-scan
CLAMP operation
HIGHZ
11111100
All outputs in
high-impedance state
simultaneously
IDCODE
11111110 Enables shifting out
32-bit IDCODE
USERCODE
11111101 Enables shifting out
32-bit USERCODE
XQ(R)18V04 Specific Instructions
CONFIG
11101110
Initiates FPGA
configuration by pulsing
CF pin Low
DS082 (v1.2) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5

5 Page





XQ18V04VQ44N arduino
R QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3V. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V VCC power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (VCC), and the output power supply
(VCCO) may have power applied in any order. This makes
the PROM devices immune to power supply sequencing
issues.
is held low until the XQ(R)18V04 voltage reaches the oper-
ating voltage range. If the power drops below 2.0V, the
PROM will reset. OE/RESET polarity is NOT programma-
ble.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input. JTAG pins
TMS, TDI and TDO can be in a high-impedance state or
High.
Reset Activation
On power up, OE/RESET is held low until the XQ(R)18V04
is active (1 ms) and able to supply data after receiving a
CCLK pulse from the FPGA. OE/RESET is connected to an
external resistor to pull OE/RESET HIGH releasing the
FPGA INIT and allowing configuration to begin. OE/RESET
Customer Control Pins
The XQ(R)18V04 PROMs have various control bits accessi-
ble by the customer. These can be set after the array has
been programmed using "Skip User Array" in Xilinx JTAG
Programmer Software.
Table 6: Truth Table for PROM Control Inputs
Control Inputs
Outputs
OE/RESET
High
CE
Low
Internal Address
If address < TC(1): increment
If address > TC(1): dont change
DATA
Active
High-Z
CEO
High
Low
ICC
Active
Reduced
Low Low
Held reset
High-Z
High
Active
High
High
Held reset
High-Z
High
Standby
Low High
Held reset
High-Z
High
Standby
Notes:
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
DS082 (v1.2) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
11

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