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Philips Semiconductors
N-channel TrenchMOS™ transistor
Product specification
IRF540, IRF540S
FEATURES
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 100 V
ID = 23 A
RDS(ON) ≤ 77 mΩ
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
• T.V. and computer monitor power supplies
The IRF540 is supplied in the SOT78 (TO220AB) conventional leaded package.
The IRF540S is supplied in the SOT404 (D2PAK) surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
2 drain1
3 source
tab drain
1 23
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
100
100
± 20
23
16
92
100
175
UNIT
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 package
August 1999
1
Rev 1.100
Philips Semiconductors
N-channel TrenchMOS™ transistor
Product specification
IRF540, IRF540S
Drain current, ID (A)
30
28 VDS > ID X RDS(ON)
26
24
22
20
18
16
14
12
10 175 C
8
6
4
2
0
Tj = 25 C
01234567
Gate-source voltage, VGS (V)
8
9
Fig.7. Typical transfer characteristics.
ID = f(VGS)
10
Transconductance, gfs (S)
20
VDS > ID X RDS(ON)
18
16
Tj = 25 C
14 175 C
12
10
8
6
4
2
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Threshold Voltage, VGS(TO) (V)
4.5
4 maximum
3.5
3 typical
2.5
2 minimum
1.5
1
0.5
0
-60 -40 -20
0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1.0E-01 Drain current, ID (A)
1.0E-02
1.0E-03
1.0E-04
1.0E-05
minimum
typical
maximum
1.0E-06
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Capacitances, Ciss, Coss, Crss (pF)
10000
1000
Ciss
Coss
100
Crss
10
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
5
Rev 1.100