|
|
Número de pieza | IR3Y48M | |
Descripción | CCD Signal Process & Digital Interface IC | |
Fabricantes | Sharp Electrionic Components | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de IR3Y48M (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! IR3Y48M
IR3Y48M
CCD Signal Process & Digital Interface IC
DESCRIPTION
The IR3Y48M is a CMOS single-chip signal
processing IC for CCD area sensors which includes
correlated double sampling circuit (CDS), clamp
circuit, automatic gain control amplifier (AGC),
reference voltage generator, black level detection
circuit, 20 MHz 10-bit analog-to-digital converter
(ADC), timing circuit for internally required pulses,
and serial interface for internal circuits.
FEATURES
• Low power consumption :
110 mW (TYP.) at 20 MHz mode
• Wide AGC range : 0 to 36 dB
(Gain step : 0.094 dB/step)
• High speed sample-and-hold circuits :
pulse width 10 ns (MIN.)
• Power save operation :
84 mW (TYP.) at 15 MHz mode
• Standby mode : less than 0.3 mW
• Built-in serial interface
• 10-bit ADC operating up to 20 MHz
– Non-linearity
DNL : 0.6 LSB (TYP.)
INL : 1.5 LSB (TYP.)
• Maximum input level of CCD signals : 1.1 Vp-p
• Accepts a direct signal input to ADC or AGC
(input level : 1 Vp-p (TYP.))
• Single +3 V power supply
• Package :
48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch
PIN CONNECTIONS
48-PIN QFP
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
AVDD4 2
NC 3
VRN 4
VRP 5
AVDD2 6
AVDD2 7
AVSS2 8
AVSS2 9
VCOM 10
CCDIN 11
REFIN 12
36 OP
35 RESETN
34 AVDD3
33 AVSS3
32 STBYN
31 CSN
30 SDATA
29 SCK
28 OBP
27 CCDCLP
26 BLK
25 ADCLP
13 14 15 16 17 18 19 20 21 22 23 24
(QFP048-P-0707)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
1 page IR3Y48M
PIN NO. SYMBOL
37 DO0
38 DO1
I/O
O
O
EQUIVALENT CIRCUIT
VDD
DESCRIPTION
ADC digital output (LSB).
(Capable of High-Z)
ADC digital output.
(Capable of High-Z)
39 DO2
O
ADC digital output.
(Capable of High-Z)
40 DO3
41 DO4
O
O
ADC digital output.
GND (Capable of High-Z)
ADC digital output.
(Capable of High-Z)
42 DVSS
–
Digital output driver GND. A digital
grounding pin.
43 DVDD
–
Digital output driver power supply.
(2.7 to 3.6 V)
44 DO5
45 DO6
O
O
ADC digital output.
(Capable of High-Z)
VDD ADC digital output.
(Capable of High-Z)
46 DO7
O
ADC digital output.
(Capable of High-Z)
47 DO8
48 DO9
O
O
ADC digital output.
GND (Capable of High-Z)
ADC digital output (MSB).
(Capable of High-Z)
NOTES :
• NC pins are recommended to be connected to AVSS on PCB even they are not connected electrically in the chip.
• High-Z at standby.
5
5 Page A/D Converter Circuit
IR3Y48M integrates 20 MHz 10-bit full pipeline A/D
converter (ADC).
A/D CONVERSION RANGE
The analog input range of the ADC is determined
by VREF circuit integrated in IR3Y48M. At ADC
direct input (ADIN) mode (Mode (1) Register D5 =
1), feed 1 Vp-p (full scale) signal based on clamp
level as zero reference into ADIN input pin.
A/D CONVERTER OUTPUT CODE
(AT MODE (1) REGISTER D5 = 1)
The digital output format is binary.
Thus, "all zero" digital output with zero reference
input (ADIN = CLPCAP), "all one" digital output with
full-scale input (ADIN = CLPCAP + 1 V (TYP.)).
CLOCK, PIPELINE DELAY AND OUTPUT DIGITAL
DATA TIMING
The A/D conversion is performed based on the
clock fed to ADCK pin.
The track-and-hold operation is completed at falling
(when not inverted) edge of ADCK.
The 10-bit width parallel data is obtained at rising
edge after 5.5 clock pipeline delay. (Sampling edge
is selectable by register setting.)
CODE AT CLAMP LEVEL
(AT MODE (1) REGISTER D5 = 0, D4 = 1)
The output code at clamp level can be set
throughout (1 to) 16 to 127 LSB at the step of 1
LSB by register setting.
IR3Y48M
ADC OUTPUT CODE LOGIC
ADC digital output is High-Z under following
conditions :
q Set ADC output register to 1
w Set SYBYN pin low
e Power down (by STBYN or register control)
DIGITAL OUTPUT CODE
According to ADIN, digital codes are determined as
follows :
Data Output at Straight Binary
[Mode (1) Register D2 = 0, D5 = 1]
ADIN
DIGITAL CODE
MSB
LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Clamp
reference + 1 V
1
1
1
1
1
1
1
1
1
1
::
: 1000000000
: 0111111111
:
Clamp
reference
:
0000000000
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet IR3Y48M.PDF ] |
Número de pieza | Descripción | Fabricantes |
IR3Y48 | CCD Signal Process & Digital Interface IC | Sharp Electrionic Components |
IR3Y48A1 | CCD SIGNAL PROCESS & DIGITAL INTERFACE IC | Sharp Electrionic Components |
IR3Y48M | CCD Signal Process & Digital Interface IC | Sharp Electrionic Components |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |