PDF IR3Y38 Data sheet ( Hoja de datos )

Número de pieza	IR3Y38
Descripción	CCD Signal Process & Digital Interface IC
Fabricantes	Sharp Electrionic Components
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No Preview Available ! IR3Y38M IR3Y38M CCD Signal Process & Digital Interface IC DESCRIPTION The IR3Y38M is a bipolar single-chip signal processing IC for CCD area sensors which includes correlated double sampling circuit (CDS), clamp circuit, automatic gain control amplifier (AGC), reference voltage generator, black level detection circuit, 10-bit analog-to-digital converter (ADC), and serial interface for internal circuits. FEATURES • Low power consumption : 315 mW (TYP.) • Wide AGC range : 12 to 43.5 dB • High speed sample-and-hold circuits : pulse width 12 ns (MIN.) • Built-in standby mode for power saving applications • Built-in serial interface to control the AGC gain, maximum gain and offset adjustment • 10-bit ADC operating up to 18 MHz • Digital interface for operating 3.3 V logic ICs • Single +5 V power supply • Package : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch PIN CONNECTIONS 48-PIN QFP TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 DO0 1 DO1 2 DO2 3 DO3 4 DO4 5 GND6 6 VCC6 7 DO5 8 DO6 9 DO7 10 DO8 11 DO9 12 36 VCC2 35 Ô 34 OFSCTL 33 OBCAP 32 Î 31 ﬂ/H3 30 ﬂ/H2 29 ﬂ/H1 28 Â 27 ‰ 26 REFCAP 25 VCC1 13 14 15 16 17 18 19 20 21 22 23 24 (QFP048-P-0707) In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 1 page IR3Y38M PIN NO. PIN NAME VOLTAGE 25 VCC1 5.0 V 26 REFCAP 3.2 V EQUIVALENT CIRCUIT 36 k 75 µ 200 26 VCC1 DESCRIPTION Power supply pin of the CDS/AGC. Bias decoupling pin of the CDS reference clamp circuit. This pin is connected to the GND1 via a capacitor. 63 k 2 k 150 µ GND1 27 ‰ 5.0 V (open) > 2.1 V 27 < 0.7 V 110 k 200 40 µ VCC1 68 k 65 k 10 k 32 k 75 k GND1 Standby function control pin. All actions stop and the power consumption is decreased when low. The threshold voltage has 0.4 V hysteresis. Connect to the Vcc if not used. Pulse input pin of the CDS feed- 28 Â through level clamp. 29 ﬂ/H1 > 2.1 V VCC1 Signal is clamped when low. Pulse input pin of the ﬂ/H1. 50 µ Signal is sampled when low. 30 ﬂ/H2 200 Pulse input pin of the ﬂ/H2. Signal is sampled when low. 31 ﬂH3 < 0.7 V Pulse input pin of the ﬂ/H3. 100 Signal is sampled when low. GND1 Pulse input pin of the OPB clamp 32 Î and bias error amplifier. Signal is clamped when low. 20 k 3.3 k VCC2 20 k 3.3 k Clamp capacitor pin of the optical black clamp (OPB clamp) circuit. Connect to the GND2 via a 33 OBCAP 3.7 V 33 200 capacitor. 80 µ 80 µ GND2 5 5 Page CCD IN Â ﬂ/H1 ﬂ/H2 ﬂ/H3 ADCK IR3Y38M –1 ns min. 2 ns min. 12 ns min. 3 ns min. 2 ns min. 12 ns min. 5 ns min. 3 ns min. 3 ns min. 35 ns min. 12 ns min. 35 ns min. 1 ns min. 12 ns min. 25 ns min. 25 ns min. Î signal interval Ô Å OPB interval 1.5 µs min. idle transfer interval signal interval 1.5 µs min. 11 11 Page

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