PDF IR3093M Data sheet ( Hoja de datos )

Número de pieza	IR3093M
Descripción	3 PHASE OPTERON/ ATHLON/ OR VR10.X CONTROL IC
Fabricantes	International Rectifier
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No Preview Available ! IR3093 DATA SHEET 3 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC DESCRIPTION The IR3093 Control IC provides a full featured, cost effective, single chip solution to implement robust power conversion solutions for three different microprocessor families; 1) AMD’s Opteron, 2) AMD’s Athlon or 3) Intel’s VR-10.X family of processors. The user can select the appropriate VID range with a single pin. Control and 3 phase Gate Drive functions are integrated into a single cost effective IC. . In addition to CPU power, the IR3093 offers a compact, efficient solution for high current POL converters. FEATURES x 5 bit or 6 bit VID with 0.5% overall system accuracy x Selectable VID Code for AMD Opteron or Athlon or Intel VR10.X x Programmable Slew Rate response to “On-the-Fly” VID Code Changes x 3A GATELX Pull Down Drive Capability x Programmable 100KHz to 540KHz oscillator x Programmable Voltage Positioning (can be disabled) x Programmable Softstart x Programmable Hiccup Over-Current Protection with Delay to prevent false triggering x Simplified Powergood provides indication of proper operation and avoids false triggering x Operates up to 21V input with 7.9V Under-Voltage Lockout x 5V UVL with 4.36V Under-Voltage Lockout threshold x Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage x Enable Input x OVP Flag Output detects high side fet short at powerup x Pin compatible with IR3092, 2-phase PWM Control IC x Available 48L MLPQ package ORDERING INFORMATION * Samples Only Device IR3093MTR IR3093M Order Quantity 3000 per Reel 100 piece strips PACKAGE INFORMATION VID3 VID4 ROSC VOSNS- OCSET VDAC VDRP FB EAOUT SS/DEL SCOMP2 SCOMP3 IR3093 48LD MLPQ GAT EH1 PGND1 GAT EL1 VCCL1_2 5VUVL GAT EL2 PGND2 GAT EH2 VCCH2 VCCH3 GAT EH3 PGND3 48L MLPQ (7 x 7 mm Body) – JA = 27oC/W Page 1 of 39 07/15/04 1 page IR3093 PARAMETER VDRP Buffer Amplifier cont. Source Current Sink Current Oscillator Switching Frequency Phase Shift BIASOUT Regulator SETBIAS Bias Current Set Point Accuracy BIASOUT Dropout Voltage BIASOUT Current Limit Soft Start and Delay SS/DEL to FB Input Offset Voltage Charge Current Hiccup Discharge Current OC Discharge Current Charge/Discharge Current Ratio Charge Voltage Delay Comparator Threshold Discharge Comparator Threshold Over-Current Comparator Input Offset Voltage OCSET Bias Current Max OCSET Set Point Under-Voltage Lockout VCC Start Threshold VCC Stop Threshold VCC Hysteresis 5VUVL Start Threshold 5VUVL Stop Threshold 5VUVL Hysteresis TEST CONDITION RROSC = 47k Sequence: GATEH1-GATEH2-GATEH3 RROSC = 47k V(SETBIAS)-V(BIASOUT) @ 100mA I(BIASOUT)=100mA,Threshold when V(SETBIAS)-V(BIASOUT)=0.45V With FB = 0V, adjust V(SS/DEL) until EAOUT drives high Relative to Charge Voltage V(OCSET)-V(VDAC), CSINM=CSINP1=CSINP2=CSINP3, Note 1. RROSC = 47k Start – Stop Start – Stop MIN 4 200 160 102 94 0.1 1.2 150 0.8 30 3.5 25 9 3.8 190 170 -125 23.5 3.9 7.4 6.9 400 4.05 3.92 100 TYP MAX UNIT 8 20 mA 300 650 PA 200 240 kHz 120 138 ° 103 117.5 0.25 0.55 1.8 2.5 250 450 PA V V mA 1.1 1.8 V 60 90 PA 6 9 PA 55 70 PA 10 13 PA/PA 4.0 4.2 V 250 300 mV 265 350 mV 0 125 mV 27 29.4 7.9 8.4 7.4 7.9 540 700 4.36 4.55 4.17 4.33 200 250 PA V V V mV V V mV Page 5 of 39 07/15/04 5 Page IR3093 PWM Operation The IR3093 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage control loop. The PWM block diagram of the IR3093 is shown in Figure 2. CDAC RDAC OVPSNS VDAC U30 IROSC CLK1 CLK2 CLK2 CLK3 CLK3 OSCBLOCK 80mV BB DISABLE VOSNS- VDAC ERROR AMPLIFIER PWM COMPARATOR - + RSFF S Q QB R RESET DOMINANT I R OSC / 2 9p 0.6V FB CCOMP RCOMP EAOUT IROSC RDRP VDRP VDRP BUFFER RFB SCOMP2 0. 47V 0% DUTY CYCLE CLK2 PWM COMPARATOR RSFF S Q - QB R + RESET DOMINANT IROSC Share Adjust Error Amp + - 0 TO IROSC3/4 9p 0.6V CSC2 RSC2 RSFF CLK3 S PWM COMPARATOR Q EAOUT - QB R + RESET DOMINANT IROSC SCOMP3 CSC3 RSC3 Share Adjust Error Amp + - 0 TO IROSC*3/4 9p 0.6V VDAC VDAC VDAC X23.5 - + X23.5 - + X23.5 - + GATEH1 VIN GATEL1 12 RCS1 CCS1 GATEH2 GATEL2 VIN 12 RCS2 CCS2 GATEH3 GATEL3 VIN 12 RCS3 CCS3 C SI NM3 C SI NP3 C SI NM2 C SI NP2 C SI NM1 C SI NP1 VOUT SENSE+ VOUT+ COUT VOUT- VOUT SENSE- Figure 2 – PWM Block Diagram Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 9pf capacitor is charged by a current source that proportional to the switching frequency resulting in a ramp rate of 50mV per percent duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude is typically 500mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM ramp voltage exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns off the high side driver, turns on the low side driver, and discharges the PWM ramp to 0.6V until the next clock pulse. Page 11 of 39 07/15/04 11 Page

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