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PDF IR3092 Data sheet ( Hoja de datos )

Número de pieza IR3092
Descripción 2 PHASE OPTERON/ ATHLON/ OR VR10.X CONTROL IC
Fabricantes International Rectifier 
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IR3092
DATA SHEET
2 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
DESCRIPTION
The IR3092 Control IC provides a full featured, single chip solution to implement robust power conversion
solutions for three different microprocessor families; 1) AMD Opteron, 2) AMD Athlon or 3) Intel VR10.X
family of processors. The user can select the appropriate VID range with a single pin. PWM Control and 2
phase gate drive functions are integrated into a single IC. In addition to CPU power, the IR3092 offers a
compact, efficient solution for high current POL converters.
FEATURES
x 5 bit or 6 bit VID with 0.5% overall system accuracy
x Selectable VID Code for AMD Opteron, AMD Athlon or Intel VR10.X
x Programmable Slew Rate response to “On-the-Fly” VID Code Changes
x 3.5A Gate Drive Capability
x Programmable 100KHz to 540KHz oscillator
x Programmable Voltage Positioning (can be disabled)
x Programmable Softstart
x Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
x Simplified Powergood provides indication of proper operation and avoids false triggering
x Operates up to 21V input with 7.8V Under-Voltage Lockout
x 5V UVL with 4.3V Under-Voltage Lockout threshold
x Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage
x Enable Input
x OVP Output
x Available in a 48L MLPQ package
ORDERING INFORMATION
x Samples Only
DEVICE
IR3092MTR
*IR3092M
PACKAGE INFORMATION
ORDER QUANTITY
3000 per Reel
100 piece strips
Page 1 of 37
VID3
VID4
ROSC
VOSNS-
OCSET
VDAC
VDRP
FB
EAOUT
SS/DEL
SCOMP
NC
IR3092
48LD MLPQ
GAT EH1
PGND1
GAT EL1
VCCL
5VUVL
GAT EL2
PGND2
GAT EH2
VCCH2
NC
NC
NC
48L MLPQ
(7 x 7 mm Body)
JA = 27oC/W
06/25/04

1 page




IR3092 pdf
IR3092
PARAMETER
Oscillator
Switching Frequency
Phase1 to Phase2 Shift
BIASOUT Regulator
SETBIAS Bias Current
Set Point Accuracy
BIASOUT Dropout Voltage
BIASOUT Current Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Hiccup Discharge Current
OC Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Delay Comparator Threshold
Delay Comparator Hysteresis
Discharge Comparator
Threshold
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
Max OCSET Set Point
Under-Voltage Lockout
VCC Start Threshold
VCC Stop Threshold
VCC Hysteresis
5VUVL Start Threshold
5VUVL Stop Threshold
5VUVL Hysteresis
5VUVL Input Resistance
PWRGD Output
Output Voltage
Leakage Current
Enable Input
Threshold, INTEL
Threshold, AMD
Input Resistance
Pull-up Voltage
TEST CONDITION
RROSC = 42kŸ
GATEH1 rise to GATEH2 rise
RROSC = 42kŸ
V(SETBIAS)-V(BIASOUT) @ 100mA
I(BIASOUT)=100mA,Threshold when
V(SETBIAS)-V(BIASOUT)=0.45V
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Relative to Charge Voltage
V(OCSET)-V(VDAC),
CSIN=CSINP1=CSINP2, Note 1.
RROSC = 42kŸ
Start – Stop
Start – Stop
To LGND
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
VID_SEL=0, Referenced to VOSNS-
VID_SEL=Float, Referenced to
VOSNS-
MIN TYP MAX UNIT
160 200 240 kHz
155 170 190
°
105 115 125
PA
0.1 0.3 0.55 V
1.2 1.8 2.5
V
150 300 450 mA
0.8 1.3 1.8
V
25 55 75 PA
2.5 5.5 7.5 PA
25 45 70 PA
9 10 11 PA/PA
3.8 4.0 4.2
V
200 240 280 mV
15 30 45 mV
200 260 350 mV
-125
0
125
28 30
3.95
33
7.2 7.8 8.3
6.7 7.3 7.8
450 500 750
4.05 4.3 4.55
3.92 4.125 4.33
100 175 250
24 36 72
150 300
0 10
0.4 0.6 0.8
1.3 1.5 1.7
7.5 15 20
2.4 3.0 3.7
mV
PA
V
V
V
mV
V
V
mV
kŸ
mV
PA
V
V
kŸ
V
Page 5 of 37
06/25/04

5 Page





IR3092 arduino
IR3092
R OSC
C D AC
R D AC
R OSC
VDAC
U39
IROSC
CLK1
CLK2
OSC BLOC K
CLK2
80mV
PWM COMPARATOR
-
+
R SF F
S
QB
R
RESET DOMINANT
BB DISABLE
-
+
I R OSC / 2
10p
0.7V
VOSN S-
VDAC
ERROR AMPLIFIER
FB
C C OMP
R C OMP
EAOU T
IROSC
RDRP VDRP
VDRP BUFFER
RFB
SCOMP
C SC 2
0.55V
0% DUTY CY CLE
R SF F
CLK2 S
PWM COMPARATOR
- QB
R
+ RESET DOMINANT
IROSC
Share Adjust Error Amp
+
- 0 TO IROSC*3/4
10p
0.7V
VDAC
R SC 2
VDAC
X24.5 -
+
X24.5 -
+
GATEH1
VIN
GATEL1
12
RCS1 CCS1
GATEH2
GATEL2
VIN
12
RCS2 CCS2
C SI N P2
C SI N M
C SI N P1
VOUT SENSE+
VOU T+
COUT
VOU T-
VOUT SENSE-
Figure 2 – PWM Block Diagram
The RSFF is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseconds in response
to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on
gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of the PWM
comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the
Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load
step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will
increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing
the output capacitor requirements.
Page 11 of 37
06/25/04

11 Page







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