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PDF IPM6220EVAL1 Data sheet ( Hoja de datos )
| Número de pieza | IPM6220EVAL1 | |
| Descripción | Advanced Triple PWM Only Mode and Dual Linear Power Controller for Portable Applications | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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NOTTMRREECICSOOLM6MD2MMa3tE2EaNN(SADDhvEEaeDDielaFtRbOEleRPFLNeAEbCW.E2MD00EE4NS)ITGNS
June 2001
ISL6235
FN9029
Advanced Triple PWM Only Mode and
Dual Linear Power Controller for Portable
Applications
The ISL6235 provides a highly integrated power control and
protection solution for five output voltages required in high-
performance notebook PC applications. The IC integrates
three fixed frequency pulse-width-modulation (PWM)
controllers and two linear regulators along with monitoring
and protection circuitry into a single 24 lead SSOP package.
The two PWM controllers that regulate the system main 5V
and 3.3V voltages are implemented with synchronous-
rectified buck converters. Synchronous rectification insures
high efficiency over a wide range of input voltage and load
variation. Efficiency is further enhanced by using the lower
MOSFET’s rDS(ON) as the current sense element. Input
voltage feed-forward ramp modulation, current-mode
control, and internal feed-back compensation provide fast
and stable handling of input voltage load transients
encountered in advanced portable computer chip sets.
The third PWM controller is a boost converter that regulates
a resistor selectable output voltage of nominally 12V.
Two internal linear regulators provide +5V ALWAYS and
+3.3V ALWAYS low current outputs required by the
notebook system controller.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
ISL6235CA
-10 to 85 24 Ld SSOP
IPM6220EVAL1 Evaluation Board
PKG.
NO.
M24.15
Pinout
ISL6235 (SSOP)
TOP VIEW
VBATT 1
3.3V ALWAYS 2
BOOT2 3
UGATE2 4
PHASE2 5
5V ALWAYS 6
LGATE2 7
PGND2 8
ISEN2 9
VSEN2 10
SDWN2 11
PGOOD 12
24 BOOT1
23 UGATE1
22 PHASE1
21 ISEN1
20 LGATE1
19 PGND1
18 VSEN1
17 SDWN1
16 GATE3
15 VSEN3
14 GND
13 SDWNALL
Features
• PWM Only Mode for Reduced Noise at Light Loads
• Provides Five Regulated Voltages
- +5V ALWAYS
- +3.3V ALWAYS
- +5V Main
- +3.3V Main
- +12V
• High Efficiency Over Wide Line and Load Range
- Synchronous Buck Converters on Main Outputs
• No Current-Sense Resistor Required
- Uses MOSFET’s rDS(ON)
- Optional Current-Sense Resistor for More Precision
• Operates Directly From Battery 5.6 to 24V Input
• Input Undervoltage Lock-Out (UVLO)
• Excellent Dynamic Response
- Voltage Feed-Forward and Current-Mode Control
• Monitors Output Voltages
• Synchronous Converters Operate Out of Phase
• Separate Shut-Down Pins for Advanced Configuration and
Power Interface (ACPI) Compatibility
• 300kHz Fixed Switching Frequency on Main Outputs
• Thermal Shut-Down Protection
Applications
• Mobile PCs
• Hand-Held Portable Instruments
• LCD PCs
• Cable Modems
• DSL Modems
• Set Top Box
Related Literature
• Application Note AN9915 (IPM6220)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1 page  
ISL6235
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic (Continued)
PARAMETER
SYMBOL
Internal Resistance to GND on VSNS2 Pin
RVSNS2
PWM1 and PWM2 CONTROLLER GATE DRIVERS
TEST CONDITIONS
MIN TYP MAX UNITS
- 66K -
Ω
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
PWM 3 CONVERTER
R2UGPUP
R2UGPDN
R2LGPUP
R2LGPDN
- 5 12
- 4 10
- 69
- 58
Ω
Ω
Ω
Ω
12V Feedback Regulation Voltage
VSEN3
- 2.472 -
V
12V Feedback Regulation Voltage Input
Current
IVSEN3
- 0.1 1.0
µA
Line and Load Regulation
0.0 < IVOUT3 < 120mA, 4.9V < 5VMain < 5.1V -2 - +2
%
Undervoltage Shut-Down Level
Overvoltage Threshold
PWM3 Oscillator Frequency
Maximum Duty Cycle
VUV3
VOVP3
Fc3
2µs Delay, % Feedback Voltage at VSNS3 Pin
2µs Delay, % Feedback Voltage at VSNS3 Pin
70
-
85
-
75 80
115 120
100 115
33 -
%
%
kHz
%
PWM 3 CONTROLLER GATE DRIVERS
Pull-Up Resistance
R3GPUP
- 8 12
Ω
Pull-Down Resistance
R3GPDN
- 8 12
Ω
5V AND 3.3V ALWAYS
Linear Regulator Accuracy
PWM1, 5V Output OFF (SDWN1 = 0V);
5.6V < VBATT < 22V; 0 < Iload < 50mA
-2.0 0.5 +2.0
%
5V ALWAYS Output Voltage Regulation
PWM1, 5V output ON (SDWN1 = 5V);
0 < Iload < 50mA
-3.3 1.0 +2.0
%
Maximum Output Current
Combined 5V ALWAYS and 3.3V ALWAYS 50 - - mA
Current Limit
Combined 5V ALWAYS and 3.3V ALWAYS
100 180
-
mA
5V ALWAYS Undervoltage Shut-Down
- 75 -
%
Bypass Switch rDS(ON)
POWER GOOD AND CONTROL FUNCTIONS
PWM1, 5V output ON (SDWN1 = 5V)
- 1.3 -
Ω
Power Good Threshold for PWM1 and
PWM2 Output Voltages
-14 -12 -10
%
PGOOD Leakage Current
PGOOD Voltage Low
PGOOD Minimum Pulse Width
SDWN1, 2- Low (Off)
IPGLKG
VPGOOD
TPGmin
VPULLUP = 5.0V
IPGOOD = -4mA
- - 1.0
- 0.2 0.5
- 10 -
- 0.8 -
µA
V
µs
V
SDWN1, 2, - High (On)
- 4.3 -
V
SDWNALL - High (On)
- 2.4 -
V
SDWNALL - Low (Off)
Over-Temperature Shutdown
Over-Temperature Hysteresis
SDWNALL
- 40 -
- 150 -
- 25 -
mV
oC
oC
5
5 Page 
ISL6235
5
4.5
4
IN-PHASE
3.5
3 OUT-OF-PHASE
2.5 5V
2
1.5
3.3V
1
0.5
0
012345
3.3V AND 5V LOAD CURRENT
INPUT CAPACITANCE RMS CURRENT AT VIN = 10.8V
FIGURE 4. INPUT RMS CURRENT VS LOAD
Use a mix of input bypass capacitors to control the voltage
ripple across the MOSFETs. Use ceramic capacitors for the
high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors can be placed very
close to the upper MOSFET to suppress the voltage induced
in the parasitic circuit impedances.
For board designs that allow through-hole components, the
Sanyo OS-CONTM series offer low ESR and good
temperature performance.
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be
capable of handling the surge-current at power-up. The TPS
series available from AVX is surge current tested.
+12V Boost Converter Inductor Selection
The inductor value is chosen to provide the required output
power to the load.
Lmax= V-----i--n----m-----i--n---2-----×-----D-----m-----a----x---2----×-----R-----o--
2 × Vo2 × F
(EQ. 9)
where, Vinmin is the minimum input voltage, 4.9V; Dmax =
1/3, the maximum duty cycle; Ro is the minimum load
resistance; Vo is the nominal output voltage and F is the
switching frequency, 100kHz.
Or, for L in uH, the maximum output current is nominally:
Imax= --1---3---.--8---8---
L × Vo
(EQ. 10)
+12V Boost Converter Output Capacitor Selection
The total capacitance on the 12V output should be chosen
appropriately, so that the output voltage will be higher than
the undervoltage limit (9V) when the 5V Main soft-start time
has elapsed. This will avoid triggering of the 12V
undervoltage protection.
The maximum value of the boost capacitor, Comax that will
charge to 9V in the soft start time, TSS, is shown below,
where L is the value of the boost inductor.
Comax
=
T-----s---s-
L
×
0.115 µ F
(EQ. 11)
The output capacitor ESR and the boost inductor ripple
current determines the output voltage ripple. The ripple
voltage is given by:
VRIPPLE = ∆IL × ESR
(EQ. 12)
and the maximum ripple current, ∆IL, is given by:
∆IL
=
5----V---
L
× 3.3µ
(EQ. 13)
where L is the boost inductor calculated above, 5V is the
boost input voltage and 3.3µ is the maximum on time for the
boost MOSFET.
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
selected based upon rDS(ON) , gate supply requirements,
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
PUPPER
=
I--O-----2----×-----r--D----S----(--O-----N----)---×-----V----O-----U----T-- + -I-O------×-----V----I--N-----×-----t--S----W------×-----F----S--
VIN
2
(EQ. 14)
PLOWER
=
I--O-----2----×-----r--D----S----(--O-----N----)---×-----(---V----I--N-----–----V-----O----U----T----)
VIN
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
dissipated by the ISL6235 and do not heat the MOSFETs.
However, a large gate-charge increases the switching time,
tSW which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet IPM6220EVAL1.PDF ] | |
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