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PDF IP82C55A-5 Data sheet ( Hoja de datos )

Número de pieza IP82C55A-5
Descripción CMOS Programmable Peripheral Interface
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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82C55A
June 1998
CMOS Programmable
Peripheral Interface
Features
Description
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Ordering Information
PART NUMBERS
TEMPERATURE PKG.
5MHz
8MHz PACKAGE
RANGE
NO.
CP82C55A-5
IP82C55A-5
CP82C55A
0oC to 70oC
IP82C55A 40 Ld PDIP -40oC to 85oC
E40.6
E40.6
CS82C55A-5
IS82C55A-5
CS82C55A
0oC to 70oC
IS82C55A 44 Ld PLCC -40oC to 85oC
N44.65
N44.65
CD82C55A-5 CD82C55A
ID82C55A-5
ID82C55A
40 Ld
CERDIP
MD82C55A-5/B MD82C55A/B
0oC to 70oC
-40oC to 85oC
-55oC to 125oC
F40.6
F40.6
F40.6
8406601QA 8406602QA SMD#
F40.6
MR82C55A-5/B
MR82C55A/B
44 Pad
CLCC
-55oC to 125oC J44.A
8406601XA 8406602XA SMD#
J44.A
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Pinouts
82C55A (DIP)
TOP VIEW
82C55A (CLCC)
TOP VIEW
PA3 1
PA2 2
PA1 3
PA0 4
RD 5
CS 6
GND 7
A1 8
A0 9
PC7 10
PC6 11
PC5 12
PC4 13
PC0 14
PC1 15
PC2 16
PC3 17
PB0 18
PB1 19
PB2 20
40 PA4
39 PA5
38 PA6
37 PA7
36 WR
35 RESET
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 VCC
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
6 5 4 3 2 1 44 43 42 41 40
GND 7
NC 8
A1 9
A0 10
PC7 11
PC6 12
PC5 13
PC4 14
PC0 15
PC1 16
PC2 17
39 NC
38 RESET
37 D0
36 D1
35 D2
34 D3
33 D4
32 D5
31 D6
30 D7
29 NC
18 19 20 21 22 23 24 25 26 27 28
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
82C55A (PLCC)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 1920 21 22 23 24 25 26 27 28
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 2969.2

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IP82C55A-5 pdf
82C55A
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display compu-
tational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal defi-
nition vs. PC layout and complete functional flexibility to sup-
port almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
XX X
DON’T
CARE
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
01234567
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2
BIT SET/RESET FLAG
0 = ACTIVE
FIGURE 5. BIT SET/RESET FORMAT
Interrupt Control Functions
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using the
bit set/reset function of port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode se-
lection and device Reset.
Operating Modes
Mode 0 (Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply writ-
ten to or read from a specific port.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
• Input are not latched
• 16 different Input/Output configurations possible
MODE 0 PORT DEFINITION
A
D4 D3
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
B GROUP A
GROUP B
PORT C
PORT C
D1 D0 PORT A (Upper) # PORT B (Lower)
0 0 Output Output 0 Output Output
0 1 Output Output 1 Output Input
1 0 Output Output 2 Input Output
1 1 Output Output 3 Input Input
0 0 Output Input 4 Output Output
0 1 Output Input 5 Output Input
1 0 Output Input 6 Input Output
1 1 Output Input 7 Input Input
0 0 Input Output 8 Output Output
0 1 Input Output 9 Output Input
1 0 Input Output 10 Input Output
1 1 Input Output 11 Input Input
0 0 Input Input 12 Output Output
0 1 Input Input 13 Output Input
1 0 Input Input 14 Input Output
1 1 Input Input 15 Input Input
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IP82C55A-5 arduino
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
11
1/0 1/0 1/0
82C55A
PC2-PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
GROUP B MODE
0 = MODE 0
1 = MODE 1
FIGURE 11. MODE CONTROL WORD
WR
RD
PC3
INTRA
PA7-PA0 8
INTE
1
PC7
PC6
OBFA
ACKA
INTE
2
PC4
PC5
STBA
IBFA
PC2-PC0 3 I/O
FIGURE 12. MODE 2
DATA FROM
CPU TO 82C55A
WR
OBF
INTR
ACK
STB
tWOB
tST
tAOB
tAK
IBF
PERIPHERAL
BUS
tSIB
tPS
tPH
tAD tKD
tRIB
RD
DATA FROM
DATA FROM
PERIPHERAL TO 82C55A
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD ÷ OBF
MASK ACK WR)
FIGURE 13. MODE 2 (BI-DIRECTIONAL)
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