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PDF IP82C54-10 Data sheet ( Hoja de datos )

Número de pieza IP82C54-10
Descripción CMOS Programmable Interval Timer
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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82C54
March 1997
CMOS Programmable Interval Timer
Features
Description
• 8MHz to 12MHz Clock Input Frequency
• Compatible with NMOS 8254
- Enhanced Version of NMOS 8253
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Status Read Back Command
• Binary or BCD Counting
• Fully TTL Compatible
• Single 5V Power Supply
• Low Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz
• Operating Temperature Ranges
- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C54 is a high performance CMOS Program-
mable Interval Timer manufactured using an advanced 2
micron CMOS process.
The 82C54 has three independently programmable and
functional 16-bit counters, each capable of handling clock
input frequencies of up to 8MHz (82C54) or 10MHz
(82C54-10) or 12MHz (82C54-12).
The high speed and industry standard configuration of the
82C54 make it compatible with the Intersil 80C86, 80C88,
and 80C286 CMOS microprocessors along with many other
industry standard processors. Six programmable timer
modes allow the 82C54 to be used as an event counter,
elapsed time indicator, programmable one-shot, and many
other applications. Static CMOS circuit design insures low
power operation.
The Intersil advanced CMOS process results in a significant
reduction in power with performance equal to or greater than
existing equivalent products.
Pinouts
82C54 (PDIP, CERDIP, SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CLK 0 9
OUT 0 10
GATE 0 11
GND 12
24 VCC
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT 1
82C54 (PLCC/CLCC)
TOP VIEW
4 3 2 1 28 27 26
D4 5
D3 6
D2 7
D1 8
D0 9
CLK 0 10
NC 11
25 NC
24 CS
23 A1
22 A0
21 CLK2
20 OUT 2
19 GATE 2
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
File Number 2970.1

1 page




IP82C54-10 pdf
82C54
Operational Description
General
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is pro-
grammed. Each Counter must be programmed before it can
be used. Unused counters need not be programmed.
Programming the 82C54
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word spec-
ifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
A1 A0
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
I/OR I/OW
8
A1 A0 CS
COUNTER
0
D0 - D7
82C54
COUNTER
1
RD WR
COUNTER
2
OUT GATE CLK OUT GATE CLK OUT GATE CLK
SC - Select Counter
SC1 SC0
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Read-Back Command (See Read Operations)
RW - Read/Write
RW1 RW0
0 0 Counter Latch Command (See Read Operations)
0 1 Read/Write least significant byte only.
1 0 Read/Write most significant byte only.
1 1 Read/Write least significant byte first, then most
significant byte.
M - Mode
M2 M1
00
00
X1
X1
10
10
M0
0 Mode 0
1 Mode 1
0 Mode 2
1 Mode 3
0 Mode 4
1 Mode 5
BCD - Binary Coded Decimal
0 Binary Counter 16-bit
1 Binary Coded Decimal (BCD) Counter (4 Decades)
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
FIGURE 4. 82C54 SYSTEM INTERFACE
Possible Programming Sequence
Write Operations
The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For Each Counter, the Control Word must be written
before the initial count is written.
2. The initial count must follow the count format specified in the
Control Word (least significant byte only, most significant byte
only, or least significant byte and then most significant byte).
Since the Control Word Register and the three Counters have
separate addresses (selected by the A1, A0 inputs), and each
Control Word specifies the Counter it applies to (SC0, SC1 bits),
no special instruction sequence is required. Any programming
sequence that follows the conventions above is acceptable.
Control Word - Counter 0
LSB of Count - Counter 0
MSB of Count - Counter 0
Control Word - Counter 1
LSB of Count - Counter 1
MSB of Count - Counter 1
Control Word - Counter 2
LSB of Count - Counter 2
MSB of Count - Counter 2
Possible Programming Sequence
Control Word Format
A1, A0 = 11; CS = 0; RD = 1; WR = 0
Control Word - Counter 0
Control Word - Counter 1
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
Control Word - Counter 2
LSB of Count - Counter 2
A1 A0
11
00
00
11
01
01
11
10
10
A1 A0
11
11
11
10
4-5

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IP82C54-10 arduino
82C54
CW = 18 LSB = 3
WR
CW = 1A LSB = 3
WR
CLK
CLK
GATE
OUT
N
N
NN
0
3
00
21
0 FF FF FF
0 FF FE FD
CW = 18 LSB = 3
WR
CLK
GATE
OUT
NN
NN
0
3
0
3
0
3
0
2
0
1
0 FF
0 FF
CW = 18 LSB = 3
WR
LSB = 2
CLK
GATE
GATE
OUT
NN
N
N
N
0
3
0
2
0
1
0 FF 0
0 FF 3
CW = 1A LSB = 3
WR
CLK
GATE
OUT
NN
N
NN
N
0
3
0
2
0
3
0
2
0 0 FF
1 0 FF
CW = 1A LSB = 3
WR
LSB = 5
CLK
OUT
GATE
NN NN
0
3
0
2
0
1
0
2
0
1
0 FF
0 FF
FIGURE 13. MODE 4
Mode 5: Hardware Triggered Strobe (Retriggerable)
OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT will
go low for one CLK pulse and then go high again.
After writing the Control Word and initial count, the counter
will not be loaded until the CLK pulse after a trigger. This
CLK pulse does not decrement the count, so for an initial
count of N, OUT does not strobe low until N + 1 CLK pulses
after trigger.
A trigger results in the Counter being loaded with the initial
count on the next CLK pulse. The counting sequence is trig-
gerable. OUT will not strobe low for N + 1 CLK pulses after
any trigger GATE has no effect on OUT.
If a new count is written during counting, the current count-
ing sequence will not be affected. If a trigger occurs after the
new count is written but before the current count expires, the
Counter will be loaded with new count on the next CLK pulse
and counting will continue from there.
OUT
N
N
N
N
N
0
3
00
21
0 FF FF 0
0 FF FE 5
0
4
FIGURE 14. MODE 5
Operation Common to All Modes
Programming
When a Control Word is written to a Counter, all Control
Logic, is immediately reset and OUT goes to a known initial
state; no CLK pulses are required for this.
Gate
The GATE input is always sampled on the rising edge of
CLK. In Modes 0, 2, 3 and 4 the GATE input is level sensi-
tive, and logic level is sampled on the rising edge of CLK. In
modes 1, 2, 3 and 5 the GATE input is rising-edge sensitive.
In these Modes, a rising edge of Gate (trigger) sets an edge-
sensitive flip-flop in the Counter. This flip-flop is then sam-
pled on the next rising edge of CLK. The flip-flop is reset
immediately after it is sampled. In this way, a trigger will be
detected no matter when it occurs - a high logic level does
not have to be maintained until the next rising edge of CLK.
Note that in Modes 2 and 3, the GATE input is both edge-
and level-sensitive.
4-11

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