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PDF IP82C237 Data sheet ( Hoja de datos )

Número de pieza IP82C237
Descripción CMOS High Performance Programmable DMA Controller
Fabricantes Intersil Corporation 
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82C237
March 1997
CMOS High Performance
Programmable DMA Controller
Features
Description
• Fully Compatible with Intersil 82C37A
- 82C237 May be Used in 8MHz and 12.5MHz 82C37A
Sockets
• Optimized for 10MHz and 12.5MHz 80C286 Systems
• Special Mode Permits 16-Bit, Zero Wait State DMA
Transfers
• High Speed Data Transfers:
- Up to 6.25MBytes/sec with 12.5MHz Clock in
Normal Mode
- Up to 12.5MBytes/sec with 12.5MHz Clock in 16-Bit
Mode
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
The 82C237 is a modified version of the 82C37A. The
82C237 is fully software and pin for pin compatible with the
82C37A but provides an additional mode for 16-bit DMA
transfers, as well as enhanced speed. Each channel may be
individually programmed for 8-bit or 16-bit data transfers.
The 82C237 controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C237 is designed to be used with an external address
latch, such as the 82C82, to demultiplex the most significant
8 bits of address. An additional latch is required to
temporarily store the most significant 8 bits of data if 16-bit
memory-to-memory transfers are desired. The 82C237 can
be used with industry standard microprocessors such as
80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80,
NSC800, 80186 and others. Multimode programmability
allows the user to select from three basic types of DMA
services, and reconfiguration under program control is
possible even with the clock to the controller stopped. Each
channel has a full 64K address and word count range, and
may be programmed to autoinitialize these registers
following DMA termination (end of process).
Ordering Information
PACKAGE
PDIP
PLCC
SBDIP
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
SMD#
CLCC
SMD#
-55oC to +125oC
8MHz
CP82C237
IP82C237
CS82C237
IS82C237
CD82C237
ID82C237
MD82C237/B
5962-9054304MQA
MR82C237/B
5962-9054304MXA
12.5MHz
CP82C237-12
IP82C237-12
CS82C237-12
IS82C237-12
CD82C237-12
ID82C237-12
MD82C237-12/B
5962-9054305MQA
MR82C237-12/B
5962-9054305MXA
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-148
File Number 2965.1

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IP82C237 pdf
82C237
Functional Description
The 82C237 is an improved version of the Intersil 82C37A
DMA controller and is fully software and pin for pin compati-
ble with the 82C37A. All operational and pin descriptions of
the 82C37A apply to the 82C237 with additional features
noted in the section titled 82C237 Operation.
The 82C237 direct memory access controller is designed to
improve the data transfer rate in systems which must
transfer data from an I/O device to memory, or move a block
of memory to an I/O device. It will also perform memory-to-
memory block moves, or fill a block of memory with data
from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data
streams, which allows the 82C237 to control data movement
with software transparency.
The DMA controller is a state-driven address and control
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without
ever being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor move or repeated string
instructions. Memory-to-memory operations require
temporary internal storage of the data byte between
generation of the source and destination addresses, so
memory-to-memory transfers take place at less than half the
rate of I/O operations, but still much faster than with central
processor techniques. The maximum data transfer rates
obtainable with the 82C237 are shown in Figure 1.
The block diagram of the 82C237 is shown on page 2. The
timing and control block, priority block, and internal registers
are the main components. Figure 2 lists the name and size
of the internal registers. The timing and control block derives
internal timing from CLK input, and generates external
control signals. The Priority Encoder block resolves priority
contention between DMA channels requesting service
simultaneously.
82C237
TRANSFER
TYPE
Compressed
Normal I/O
Memory-to-
Memory
8MHz
12.5MHz
8-BIT 16-BIT 8-BIT 16-BIT UNIT
4.00 8.00 6.25 12.5 MByte/sec
2.67 5.34 4.17 8.34 MByte/sec
1.00 2.00 1.56 3.12 MByte/sec
FIGURE 1. DMA TRANSFER RATES
DMA Operation
In a system, the 82C237 address and control outputs and
data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the 82C237
drives the busses and generates the control signals to
perform the data transfer. The operation performed by
activating one of the four DMA request inputs has previously
been programmed into the controller via the Command,
Mode, Address, and Word Count registers.
For example, if a block of data is to be transferred from RAM
to an I/O device, the starting address of the data is loaded
into the 82C237 Current and Base Address registers for a
particular channel, and the length of the block is loaded into
the channel’s Word Count register. The corresponding Mode
register is programmed for a memory-to-I/O operation (read
transfer), and various options are selected by the Command
register and the other Mode register bits. The channel’s
mask bit is cleared to enable recognition of a DMA request
(DREQ). The DREQ can either be a hardware signal or a
software command.
Once initiated, the block DMA transfer will proceed as the
controller outputs the data address, simultaneous MEMR
and IOW pulses, and selects an I/O device via the DMA
acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is
transferred, the address is automatically incremented (or
decremented) and the word count is decremented. The
operation is then repeated for the next byte. The controller
stops transferring data when the Word Count register
underflows, or an external EOP is applied.
NAME
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
Command Register
Temporary Register
Mode Registers
Mask Register
Request Register
Data-Width Register (See Note)
NOTE: 82C237 only
SIZE
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
8-Bits
8-Bits
8-Bits
6-Bits
4-Bits
4-Bits
4-Bits
NUMBER
4
4
4
4
1
1
1
1
1
4
1
1
1
FIGURE 2. 82C237 INTERNAL REGISTERS
To further understand 82C237 operation, the states
generated by each CLK cycle must be considered. The DMA
controller operates in two major cycles, active and idle. After
being programmed, the controller is normally idle until a
DMA request occurs on an unmasked channel, or a software
request is given. The 82C237 will then request control of the
system busses and enter the active cycle. The active cycle is
composed of several internal states, depending on what
options have been selected and what type of operation has
been requested.
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IP82C237 arduino
82C237
Software Commands
There are special software commands which can be
executed by reading or writing to the 82C237. These com-
mands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
Clear First/Last Flip-Flop - This command is executed prior
to writing or reading new address or word count information
to the 82C237. This command initializes the flip-flop to a
known state (low byte first) so that subsequent accesses to
register contents by the microprocessor will address upper
and lower bytes in the correct sequence.
Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
Master Clear - This software instruction has the same effect
as the hardware RESET. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C237 will enter the idle cycle.
Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
Clear Mode Register Counter - Since only one address
location is available for reading the Mode registers, an inter-
nal two-bit counter has been included to select Mode regis-
ters during read operation. To read the Mode registers, first
execute the Clear Mode Register Counter command, then
do consecutive reads until the desired channel is read. Read
order is channel 0 first, channel 3 last. The lower two bits on
all Mode registers will read as ones.
External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resis-
tor to VCC is required. The value of the external pull-up
resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C237 will not accept
external EOP signals when it is in an SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C237 enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C237 is in an SI state.
16-Bit Transfer Mode
The 82C237 is fully software and pin for pin compatible with
the 82C37A. Therefore, the 82C237 may be used as a faster
82C37A without modifications to software or hardware. The
82C237 may be used as an 82C37A, however, the 82C237
has an additional feature in that it may be programmed to
perform 16-bit DMA transfers, thus doubling data transfer
rate. In 16-bit transfer mode the device operates the same
as in normal (8-bit) transfer mode with exceptions noted in
this section.
16-Bit Transfer Mode Initialization - To initialize the
82C237 to 16-bit Transfer Mode, a specific sequence of soft-
ware commands must be written to the device immediately
after a hardware RESET or a Master Clear instruction. The
sequence to initialize 16-bit Transfer Mode is as follows:
1) Hardware RESET or Master Clear
2) Set First/Last Flip-Flop
3) Clear First/Last Flip-Flop
These software commands must occur sequentially with no
communication to or from the 82C237 between commands.
Once in 16-bit mode, the device will remain in this mode until
a hardware RESET or Master Clear sets it back to normal
(8-bit) transfer mode. If this initialization sequence is not fol-
lowed exactly, the 82C237 will operate exactly like the
82C37A or the 82C237 in normal 8-bit mode.
16-Bit DMA Transfers - In 16-bit transfer mode, each DMA
channel may be programmed to perform 8-bit or 16-bit trans-
fers. Channels which are programmed to perform 8-bit trans-
fers will operate like a normal 82C37A transfer. On channels
programmed to perform 16-bit transfers, the Current
Address register, which is normally incremented or decre-
mented by one after each transfer, is incremented or decre-
mented by two after each transfer. Also, the Current Word
Count register, which is normally decremented by one after
each transfer, is decremented by two after each transfer.
16-Bit Memory-to-Memory Transfers - 16-bit memory-to-
memory transfers require an external latch to temporarily
store the 8 most significant bits of data. When 16-bit transfer
mode is enabled, Pin 5 (DWLE) becomes an active output
which may be used to enable the external data latch during
memory-to-memory operations. See Figure 9 for a 16-bit
DMA application. Channels 0 and 1 operate as memory-to-
memory transfer channels. IF either channel 0 or channel 1
is programmed to perform 16-bit transfers when a memory-
to-memory transfer is initiated, the transfer will be a 16-bit
transfer. If 8-bit memory-to-memory transfers are desired
while the 82C237 is in 16-bit transfer mode, channels 0 and
1 must both be programmed for 8-bit transfers.
Pin 5 DWLE Output - When the 82C237 is initialized to 16-
bit transfer mode, pin 5 is always high impedance three-
stated. This insures compatibility with the 82C37A pin 5
description. In 16-bit transfer mode, this output becomes
active and serves a dual purpose.
During the S1 cycle of a transfer, the DWLE output indicates
the data width (0 = 16-bit, 1 = 8-bit) of the active channel.
This signal may be used with the A0 output to generate a
High Byte Enable signal for use in chip select decode logic.
Since DWLE is a multiplexed pin, Data Width information
needs to be captured in an external latch on the falling edge
of ADSTB. See Figure 9 for a 16-bit DMA application.
During memory-to-memory transfer, the DWLE output is
used to enable an external latch which temporarily stores the
8 most significant bits of data during the read-from-memory
half of the transfer. DWLE enables this byte of data onto the
data bus during the write-to-memory half of the transfer. See
Figure 9 for a 16-bit DMA application.
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