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PDF DAC08GBC Data sheet ( Hoja de datos )

Número de pieza DAC08GBC
Descripción 8-Bit/ High-Speed/ Multiplying D/A Converter (Universal Digital Logic Interface)
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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No Preview Available ! DAC08GBC Hoja de datos, Descripción, Manual

a 8-Bit, High-Speed, Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC08
FEATURES
Fast Settling Output Current: 85 ns
Full-Scale Current Prematched to ؎1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% Maximum over
Temperature Range
High Output Impedance and Compliance:
–10 V to +18 V
Complementary Current Outputs
Wide Range Multiplying Capability: 1 MHz Bandwidth
Low FS Current Drift: ؎10 ppm/؇C
Wide Power Supply Range: ؎4.5 V to ؎18 V
Low Power Consumption: 33 mW @ ؎5 V
Low Cost
Available in Die Form
GENERAL DESCRIPTION
The DAC08 series of 8-bit monolithic digital-to-analog convert-
ers provide very high-speed performance coupled with low cost
and outstanding applications flexibility.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20-to-1 reference
current range. Matching to within 1 LSB between reference and
full-scale currents eliminates the need for full-scale trimming in
most applications. Direct interface to all popular logic families
with full noise immunity is provided by the high swing, adjust-
able threshold logic input.
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential opera-
tion to effectively double the peak-to-peak output swing. In
many applications, the outputs can be directly converted to
voltage without the need for an external op amp.
All DAC08 series models guarantee full 8-bit monotonicity,
and nonlinearities as tight as ± 0.1% over the entire operating
temperature range are available. Device performance is essen-
tially unchanged over the ± 4.5 V to ± 18 V power supply range,
with 33 mW power consumption attainable at ± 5 V supplies.
The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
applications where low cost, high speed and complete input/
output versatility are required.
FUNCTIONAL BLOCK DIAGRAM
MSB
V+ VLC B1 B2 B3 B4 B5 B6
13 1 5 6 7 8 9 10
DAC08
14
VREF (+)
BIAS
NETWORK
CURRENT
SWITCHES
15
VREF (–)
REFERENCE
AMPLIFIER
16
COMP
3
V–
B7
11
LSB
B8
12
4 IOUT
2
IOUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

1 page




DAC08GBC pdf
DAC08
WAFER TEST LIMITS (@ VS = ؎15 V, IREF = 2.0 mA; TA = 25؇C, unless otherwise noted. Output characteristics apply to both
IOUT and IOUT .)
Parameter
Symbol
Conditions
DAC08N
Limit
DAC08G
Limit
DAC08GR
Limit
Unit
Resolution
Monotonicity
Nonlinearity
Output Voltage
Compliance
Full-Scale Current
Full-Scale Symmetry
Zero-Scale Current
Output Current Range
Logic Input 0
Logic Input 1
Logic Input Current
Logic 0
Logic 1
Logic Input Swing
Reference Bias Current
Power Supply
Sensitivity
Power Supply Current
Power Dissipation
NL
VOC
IFS4 or
IFS2
IFSS
IZS
IFS1 or
IFS2
VIL
VIH
IIL
IIH
VIS
I15
PSSIFS+
PSSIFS
I+
PD
Full-Scale Current
Change < 1/2 LSB
VREF = 10.000 V
R14, R15 = 5.000 k
V= 10 V,
VREF = +15 V
V= 12 V,
VREF = +25 V
R14, R15 = 5.000 k
VLC = 0 V
VIN = 10 V to +0.8 V
VIN = +2.0 V to +18 V
V= 15 V
V+ = +4.5 V to +18 V
V= 4.5 V to 18 V
IREF = 1.0 mA
VS = ± 15 V
IREF 2.0 mA
VS = ± 15 V
IREF 2.0 mA
8
8
± 0.1
+18
10
2.04
1.94
±8
2
2.1
4.2
0.8
2
± 10
± 10
+18
10
3
0.01
3.8
7.8
174
8
8
± 0.19
+18
10
2.04
1.94
±8
4
2.1
4.2
0.8
2
± 10
± 10
+18
10
3
0.01
3.8
7.8
174
8
8
± 0.39
+18
10
2.04
1.94
± 16
4
2.1
4.2
0.8
2
± 10
± 10
+18
10
3
0.01
3.8
7.8
174
Bits min
Bits min
% FS max
V max
V min
mA max
mA min
µA max
µA max
mA min
mA min
V max
V min
µA max
µA max
V max
V min
µA max
% FS/% V max
mA max
µA max
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
–5–

5 Page





DAC08GBC arduino
DAC08
range, negative logic input range and negative logic threshold
range; consult the various figures for guidance. For example,
operation at 4.5 V with IREF = 2 mA is not recommended
because negative output compliance would be reduced to near
zero. Operation from lower supplies is possible; however, at
least 8 V total must be applied to ensure turn-on of the internal
bias network.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required: however, an artificial
ground may be used to ensure logic swings, etc., remain
between acceptable limits.
Power consumption may be calculated as follows:
PD = (I+) (V+) + (I–) (V–)
A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states; this is useful in
cryptographic applications and further serves to reduce the size
of the power supply bypass capacitors.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is low, typically ±10 ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approxi-
mately 10% at 55°C; at +125°C an increase of about 15%
is typical.
The reference amplifier must be compensated by using a capacitor
from pin 16 to V. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see Reference Amplifier Compensation for Multiplying Applica-
tionssection.
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range
of 4 µA to 4 mA. Monotonic operation is maintained over a
typical range of IREF from 100 µA to 4.0 mA.
SETTLING TIME
The DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful
board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 35 ns for each of the 8 bits.
Settling time to within 1/2 LSB of the LSB is therefore 35 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 85 ns, thus determining the overall settling time
of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08 including the package is
approximately 15 pF, therefore the output RC time constant
dominates settling time if RL > 500 .
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
Measurement of settling time requires the ability to accurately
resolve ± 4 µA, therefore a 1 kload is needed to provide
adequate drive for most oscilloscopes. The settling time fix-
ture shown in schematic labelled Settling Time Measurement
uses a cascade design to permit driving a 1 kload with less
than 5 pF of parasitic capacitance at the measurement node. At
IREF values of less than 1.0 mA, excessive RC damping of the
output is difficult to prevent while maintaining adequate sensi-
tivity. However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code change
does not require the normal 6.2 time constants to settle to
within ± 0.2% of the final value, and thus settling times may be
observed at lower values of IREF.
DAC08 switching transients or glitchesare very low and may
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time.
Fastest operation can be obtained by using short leads, minimizing
output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capacitors
at the supply pins provide full transient protection.
REV. B
VCL
0.7V
+VREF
0.1F
FOR TURN-ON, VL = 2.7V
FOR TURN-OFF, VL = 0.7V
VL
1k
MINIMUM
CAPACITANCE
Q1
VIN
1F
1k
+5V
50F
1F
Q2
VOUT 1X
PROBE
RREF
R15
14 5
15
6 7 8 9 10 11 12
4
DAC08
2
13 3 16
0.01F
IOUT
100k2k
15k
15V
+0.4V
0V
0V
0.4V
0.1F
0.1F
+15V 15V
0.1F
Figure 17. Settling Time Measurement
–11–

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