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Número de pieza ICS93716YF-T
Descripción Low Cost DDR Phase Lock Loop Clock Driver
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICS93716YF-T Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS9371 6
Low Cost DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 650ps - 950ps
Pin Configuration
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 CLKC5
26 CLKT5
25 CLKC4
24 CLKT4
23 VDD
22 SDATA
21 FBINC
20 FBINT
19 FB_OUTT
18 FB_OUTC
17 CLKT3
16 CLKC3
15 GND
28-Pin SSOP and TSSOP
Block Diagram
Functionality
AVDD
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
GND
GND
INPUTS
CLK_INT CLK_INC
LH
HL
<20MHz
LH
HL
CLKT
L
H
Z
L
H
OUTPUTS
CLKC FB_OUTT
HL
LH
ZZ
HL
LH
PLL State
FB_OUTC
H on
L on
Z off
H Bypassed/off
L Bypassed/off
SCLK
SDATA
Control
Logic
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
0420E—04/01/03
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5

1 page




ICS93716YF-T pdf
ICS9371 6
DC Electrical Characteristics (see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Voltage
Low level input voltage
VDDQ, AVDD
CLK_INT, CLK_INC, FB_INC,
VIL FB_INT
SCLK, SDATA
2.3
-0.3
High level input voltage
VIH
CLK_INT, CLK_INC, FB_INC,
FB_INT
VDD/2 + 0.18
SCLK, SDATA
1.7
DC input signal voltage
(note 2)
VIN
-0.3
Differential input signal
voltage (note 3)
DC - CLK_INT, CLK_INC,
VID
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36
0.7
Output differential cross-
voltage (note 4)
VOX
VDD/2 - 0.15
Input differential cross-
voltage (note 4)
VIX
VDD/2 - 0.2
High Impedance
Output Current
IOZ VDD=2.7V, VOUT=VDD or GND
Operating free-air
temperature
TA
0
TYP
2.5
0.4
2.1
VDD/2
0.1
MAX
2.7
UNITS
V
VDD/2 - 0.18
0.7
V
V
V
5V
VDD + 0.3
V
VDD + 0.6
V
VDD + 0.6
V
VDD/2 + 0.15 V
VDD/2 + 0.2 V
±5 µA
85 °C
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC excursion of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal crosses.
0420E—04/01/03
5

5 Page





ICS93716YF-T arduino
ICS9371 6
N
INDEX
AREA
12
D
A2
e
b
c
E1 E
L
A
A1
-C-
SEATING
PLANE
.10 (.004) C
α
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN MAX
-- 2.00
0.05 --
1.65 1.85
0.22 0.38
0.09 0.25
SEE VARIATIONS
7.40 8.20
5.00 5.60
0.65 BASIC
0.55 0.95
SEE VARIATIONS
0° 8°
In Inches
COMMON DIMENSIONS
MIN MAX
-- .079
.002 --
.065 .073
.009 .015
.0035
.010
SEE VARIATIONS
.291 .323
.197 .220
0.0256 BASIC
.022 .037
SEE VARIATIONS
0° 8°
VARIATIONS
N
D mm.
MIN MAX
28 9.90 10.50
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
D (inch)
MIN MAX
.390 .413
Ordering Information
ICS93716yF-T
Example:
ICS XXXXX y F - T
0420E—04/01/03
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
11

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