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PDF ICS9250YF-38-T Data sheet ( Hoja de datos )
| Número de pieza | ICS9250YF-38-T | |
| Descripción | Frequency Generator with 200MHz Differential CPU Clocks | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9250-38
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK 408 clock for Almador-M mobile chipset with Tualatin
PIII processor.
Pin Configuration
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 1 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
• 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
• 1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
Features:
• Almador Chipset has a DLL driving the clock buffer
path for the 3 buffer path 66.6 MHz outputs,
66Buf(0:2).
Almador board level designs MUST use pin 22,
66Buf_1, as the feedback connection from the
clock buffer path to the Almador (GMCH)
chipset.
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
66MHz_OUT0/3V66_2
66MHz_OUT1/3V66_3
66MHz_OUT2/3V66_4
66MHz_IN/3V66_5
*PD#
VDDA
GND
Vtt_PWRGD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 I REF
41 GND
40 FS2
39 48MHz_USB
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK
34 PCI_STOP#*
33 3V66_0
32 VDD3V66
31 GND
30 SCLK
29 SDATA
56-Pin 300mil SSOP/TSSOP
• Supports spread spectrum modulation,
* These inputs have 150K internal pull-up resistor to VDD.
down spread 0 to -0.5%.
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• 66MHz Output Jitter (Buffered Mode Only) <100ps
• CPU Output Skew <100ps
Functionality
Block Diagram
PLL2
X1 XTAL
X2 OSC
48MHz_USB
48MHz_DOT
3V66_1/VCH_CLK
FS2
FS1 FS0
CPU
(MHz)
3V66
(MHz)
66Buff[2:0]
3V66[4:2]
(MHz)
0 0 0 66.66 66.66 66.66
0
0
1 100.00 66.66
66.66
0 1 0 200.00 66.66 66.66
PCI_F
PCI
(MHz)
33.33
33.33
33.33
66MHz_IN
REF
0
1
1 133.33 66.66
66.66
33.33
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
1 0 0 66.66 66.66 66MHz_IN 66MHz_IN/2
1 0 1 100.00 66.66 66MHz_IN 66MHz_IN/2
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
66MHz
DIVDER
3V66
DIVDER
PCICLK (6:0)
7
PCICLK_F (2:0)
3
66MHz_OUT (2:0)
3
3V66 (5:2,0)
5
I REF
11
11
Mid 0
Mid 0
Mid 1
Mid 1
0 200.00 66.66 66MHz_IN 66MHz_IN/2
1 133.33 66.66 66MHz_IN 66MHz_IN/2
0 Tristate Tristate Tristate
Tristate
1 TCLK/2 TCLK/4 TCLK/4
TCLK/8
0 Reserved Reserved Reserved Reserved
1 Reserved Reserved Reserved Reserved
0404B—12/23/02
1 page  
ICS9250-38
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD2
1
1
1
1
1
1
1
0
Type1
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
(Reserved)
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
5
6
7
5
6
7
39
38
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK_F0
PCICLK_F1
PCICLK_F2
48MHz_USB
48MHz_DOT
PWD2
1
1
1
0
0
0
1
1
Type1
RW
RW
RW
RW
RW
RW
RW
RW
Description
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
Allow control of PCICLK_F0 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F1 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F2 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
-
Name
3V66-2
3V66-3
3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
-
PWD2
1
1
1
1
1
1
0
0
Type1
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
0=Disabled 1=Enabled 4
(Reserved)
(Reserved)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0404B—12/23/02
5
5 Page 
ICS9250-38
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
0404B—12/23/02
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS9250YF-38-T.PDF ] | |
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