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PDF ICS9248YF-189-T Data sheet ( Hoja de datos )
| Número de pieza | ICS9248YF-189-T | |
| Descripción | AMD - K7�� Clock Generator for Mobile System | |
| Fabricantes | Integrated Circuit Systems　 | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-189
Advance Information
AMD - K7â„¢ Clock Generator for Mobile System
Recommended Application:
VIA K7/KN/KX-133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - CPU clock @ 3.3V
• 7 - SDRAM @ 3.3V
• 8 - PCI @ 3.3V,
• 1 - 48MHz, @ 3.3V fixed
• 1 - 24/48MHz @ 3.3V
• 3 - REF @ 3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management via hardware select CPU
stop, CLOCK stop, PCI stop, and SDRAM stop
• Support power management via I2C programing
• Spread spectrum for EMI control
(± 0.25% to ± 0.06% center, or 0 to -0.5% or -1.0% down
spread)
• Uses external 14.318MHz crystal
Key Specifications:
• CPU - CPU Skew: <175ps
• CPU - SDRAM Skew: ±125ps
• CPU - PCI Skew: ±100ps
• PCI - PCI Skew: <500ps
Pin Configuration
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF01
47 REF1
46 REF2/FS3*
45 GND
44 GND
43 VDD
42 CPUCLK_CS
41 CPUCLKT02
40 CPUCLKC02
39 CPU_STOP#*
38 CLK_STOP#*/PD#
37 SDRAM0
36 SDRAM1
35 VDDSDR
34 GND
33 SDRAM2
32 SDRAM3
31 GND
30 VDDSDR
29 SDRAM4
28 SDRAM5
27 SDRAM_F
26 SCLK
25 SDATA
48-Pin 300mil SSOP & 240mil TSSOP
* Internal Pull-up Resistor of 120K to VDD
1 These outputs have double strength to drive 2 loads.
2 These outputs can be set to 1X or 1.5X strength
through I2C
Block Diagram
PLL2
X1
X2
SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
CLK_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
XTAL
OSC
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
PCI
DIVDER
Stop
SDRAM
DIVIDER
Stop
Functionality
48MHz
24_48MHz
REF (2:0)
3
CPUCLK_CS
CPUCLKT0
CPUCLKC0
PCICLK (6:0)
7
PCICLK_F
SDRAM (5:0)
6
SDRAM_F
FS2 FS1 FS0 CPU PCI Spread Percentage
0 0 0 100.00 33.33 +/- 0.35% Center Spread
0 0 1 133.33 33.33 +/- 0.35% Center Spread
0 1 0 100.00 33.33 0 to - 0.5% Down Spread
0 1 1 133.33 33.33 0 to - 0.5% Down Spread
1 0 0 100.00 33.33 +/- 0.6% Center Spread
1 0 1 133.33 33.33 +/- 0.6% Center Spread
1 1 0 100.00 33.33
No Spread
1 1 1 133.33 33.33
No Spread
Note: For a complete functionality table please see table in
page 3.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
9248-189 Rev - 08/10/01
Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
1 page  
ICS9248-189
Advance Information
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
Note: Don’t write into this register, writing into this
register can cause malfunction
Byte 7: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
- 0 Reserved
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-189
Advance Information
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
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