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Número de pieza ICS87004AGT
Descripción 1:4/ DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
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Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87004 is a highly versatile 1:4 Differential-
ICS to-LVCMOS/LVTTL Clock Generator and a mem-
HiPerClockS™ ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The ICS87004
has two selectable clock inputs.The CLK0, nCLK0
and CLK1, nCLK1 pairs can accept most standard differential
input levels. Internal bias on the nCLK0 and nCLK1 inputs
allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL.
The ICS87004 has a fully integrated PLL and can be configured
as zero delay buffer, multiplier or divider and has an input and
output frequency range of 15.625MHz to 250MHz. The refer-
ence divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.The exter-
nal feedback allows the device to achieve “zero delay” between
the input clock and the output clocks. The PLL_SEL pin can be
used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
BLOCK DIAGRAM
FEATURES
• 4 LVCMOS/LVTTL outputs, 7typical output impedance
• Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Internal bias on nCLK0 and nCLK1 to support
LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 45ps (maximum)
• Static phase offset: 50 ± 125ps (3.3V ± 5%)
• Full 3.3V or 2.5V operating supply
• 5V tolerant inputs
• Lead-Free package available
• Industrial temperature information available upon request
PIN ASSIGNMENT
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
÷2, ÷4, ÷8, ÷16,
÷32, ÷64, ÷128
0
1 PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
SEL0
GND 1
24 Q1
Q0
Q0 2
2 3 VDDO
VDDo 3
22 Q2
Q1
SEL0 4
SEL1 5
21 GND
20 Q3
SEL2 6
1 9 VDDO
Q2
SEL3 7
18 MR
CLK_SEL 8
17 FB_IN
VDD 9
16 PLL_SEL
Q3 CLK0 10 15 CLK1
nCLK0 11 14 nCLK1
GND 12 13 VDDA
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
G Package
Top View
SEL1
SEL2
SEL3
MR
87004AG
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 16, 2004

1 page




ICS87004AGT pdf
Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1
VDD = VIN = 3.465V,
IIH
Input High Current
nCLK0, nCLK1
VDD = VIN = 2.625V
VDD = VIN = 3.465V,
VDD = VIN = 2.625V
150
150
CLK0, CLK1
VDD = 3.465V, VIN = 0V,
IIL Input Low Current
VDD = 2.625V, VIN = 0V
V = 3.465V, V = 0V,
nCLK0, nCLK1
DD
IN
VDD = 2.625V, VIN = 0V
-5
-150
VPP
VCMR
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
0.15
GND + 0.5
1.3
VDD - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
µA
µA
µA
µA
V
V
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
VDD
VDDA
VDDO
IDD
IDDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
96
15
6
Units
V
V
V
mA
mA
mA
87004AG
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 16, 2004

5 Page





ICS87004AGT arduino
Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
70°C/W
200
63°C/W
500
60°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87004 is: 2578
87004AG
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 16, 2004

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