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PDF ICS83905AMT Data sheet ( Hoja de datos )

Número de pieza ICS83905AMT
Descripción LOW SKEW/ 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Fabricantes Integrated Circuit Systems 
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No Preview Available ! ICS83905AMT Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS83905 is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™ HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83905 single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50series or parallel terminated transmission lines.
The effective fanout can be increased from 6 to 12 by utilizing
the ability of the outputs to drive two series terminated lines.
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew char-
acteristics along with the 1.8V output capabilities makes the
ICS83905 ideal for high performance, single ended applica-
tions that also require a limited output voltage.
FEATURES
6 LVCMOS / LVTTL outputs
Crystal oscillator interface
Output frequency range: 10MHz to 50MHz
Crystal input frequency range: 10MHz to 50MHz
Output skew: 10ps (typical)
5V tolerant enable inputs
Synchronous output enables
Operating supply modes: Full 3.3V, 2.5V and 1.8V,
mixed 3.3Vcore/2.5V or1.8V operating supply, and
mixed 2.5V core/1.8V operating supply
0°C to 70°C ambient operating temperature
Lead-Free package fully RoHS compliant
Pin compatible to MPC905
Industrial version available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
XTAL_OUT
ENABLE 1
ENABLE 2
SYNCHRONIZE
SYNCHRONIZE
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
XTAL_OUT
ENABLE 2
GND
BCLK0
VDDo
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16 XTAL_IN
15 ENABLE 1
14 BCLK5
1 3 VDDO
12 BCLK4
11 GND
10 BCLK3
9 VDD
ICS83905
16-Lead SOIC
3.9mm x 9.9mm x 1.38mm body package
M Pacakge
Top View
ICS83905
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm body package
G Pacakge
Top View
GND
GND
BCLK0
VDDO
BCLK1
20 19 18 17 16
1 ICS83905 15
2 20-Lead VFQFN 14
3
4mm x 4mm x 0.9mm
body package 13
4 K Package 12
5 Top View 11
6 7 8 9 10
BCLK5
VDDO
BCLK4
GND
GND
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83905AM
http://www.icst.com/products/hiperclocks.html
REV. A JANUARY 20, 2005
1

1 page




ICS83905AMT pdf
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
Using External Crystal
f Output Frequency
MAX Using External Clock Source
10 50 MHz
DC 100 MHz
HIGH (above 2V); NOTE 1
0.5T
LOW (below 0.8V), NOTE 2
tPW
Output Pulse Width
HIGH (above 2V); NOTE 1
T = Periods
0.5T
0.5T
LOW (below 0.8V), NOTE 2
0.5T
tPER
tsk(o)
Output Period
Output Skew; NOTE 3, 5
T = desired Period
TBD
10
ps
tR/tF Output Rise/Fall Time
tEN
Output Enable Time; ENABLE 1
NOTE 4
ENABLE 2
20% to 80%
500
TBD
TBD
ps
ms
ms
t
DIS
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
TBD
TBD
ms
ms
AOSC
XTAL_IN to XTAL_OUT Oscillator Gain
Phase Loop Phase Shift Modulo 360°+
TBD
TBD
db
°
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Assuming input duty cycle specs from Recommended Operating Conditons table are met.
NOTE 2: Assuming external crystal or 50% duty cycle external reference is used.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Using External Crystal
fMAX
Output Frequency
Using External Clock Source
odc Output Duty Cycle
tPER
tsk(o)
Output Period
Output Skew; NOTE 3, 5
t /t Output Rise/Fall Time
RF
tEN
Output Enable Time; ENABLE 1
NOTE 4
ENABLE 2
20% to 80%
tDIS
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
AOSC
XTAL_IN to XTAL_OUT Oscillator Gain
Phase Loop Phase Shift Modulo 360°+
See notes from Table 5A.
Minimum Typical Maximum Units
10 50 MHz
DC 100 MHz
50 %
TBD
10 ps
500 ps
TBD
ms
TBD
ms
TBD
ms
TBD
ms
TBD
db
TBD
°
83905AM
http://www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 20, 2005

5 Page





ICS83905AMT arduino
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6A. θJAVS. AIR FLOW TABLE FOR 16 LEAD SOIC
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
78.8°C/W
1
71.1°C/W
2
66.2°C/W
TABLE 6B. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6C. θJAVS. AIR FLOW TABLE FOR 20 LEAD VFQFN
θJA by Velocity (Meters per Second)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
141.7°C/W
38.5°C/W
1
126°C/W
35°C/W
2.5
116.9°C/W
33.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83905 is: 339
83905AM
http://www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 20, 2005

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