PDF KM736V989 Data sheet ( Hoja de datos )

Número de pieza	KM736V989
Descripción	512Kx36 & 1Mx18 Synchronous SRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! KM736V989 KM718V089 512Kx36 & 1Mx18 Synchronous SRAM Document Title 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History 0.0 Initial draft 0.1 1. Update ICC & ISB values. 0.2 1. Change ISB value from 150mA to 110mA at -67. 2. Change ISB value from 130mA to 90mA at -72 . 3. Change ISB value from 120mA to 80mA at -10 . 0.3 1. Add tCYC 167MHz and 183MHz. 2. Changed DC condition at Icc and parameters Icc ; from 420mA to 400mA at -67, from 400mA to 380mA at -72, from 350mA to 320mA at -10, 1.0 1. Final Spec Release. Draft Date Remark Dec. 29. 1998 Preliminary May. 27. 1999 Preliminary Sep. 04. 1999 Preliminary Nov. 19. 1999 Preliminary Dec. 08. 1999 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. - 1 - December 1999 Rev 1.0 1 page KM736V989 KM718V089 512Kx36 & 1Mx18 Synchronous SRAM 119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) KM736V989(512Kx36) 123456 A VDDQ A A ADSP A A B NC A A ADSC A A C NC A A VDD A A D DQc DQPc VSS NC VSS DQPb E DQc DQc VSS CS1 VSS DQb F VDDQ DQc VSS OE VSS DQb G DQc DQc WEc ADV WEb DQb H DQc DQc VSS GW VSS DQb J VDDQ VDD NC VDD NC VDD K DQd DQd VSS CLK VSS DQa L DQd DQd WEd NC WEa DQa M VDDQ DQd VSS BW VSS DQa N DQd DQd VSS A1* VSS DQa P DQd DQPd VSS A0* VSS DQPa R NC A LBO VDD NC A T NC NC A A A NC U VDDQ NC NC NC NC NC Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ PIN NAME SYMBOL A A0, A1 ADV ADSP ADSC CLK CS1 WEx (x=a,b,c,d) OE GW BW ZZ LBO PIN NAME Address Inputs Burst Count Address Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control SYMBOL VDD VSS N.C. DQa DQb DQc DQd DQPa~Pd VDDQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus Output Power Supply (2.5V or 3.3V) - 5 - December 1999 Rev 1.0 5 Page KM736V989 KM718V089 Output Load(A) Dout Zo=50Ω 512Kx36 & 1Mx18 Synchronous SRAM RL=50Ω 30pF* VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) Dout +3.3V for 3.3V I/O /+2.5V for 2.5V I/O 319Ω / 1667Ω 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C) Parameter Symbol Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High Address Status Setup to Clock High Data Setup to Clock High Write Setup to Clock High (GW, BW, WEX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High Address Status Hold from Clock High Data Hold from Clock High Write Hold from Clock High (GW, BW, WEX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tSS tDS tWS tADVS tCSS tAH tSH tDH tWH tADVH tCSH tPDS tPUS -54 Min Max 5.4 - - 3.3 - 3.3 0- 1.3 - 0- - 3.0 1.3 3.0 2.0 - 2.0 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 2- 2- -60 Min Max 6.0 - - 3.5 - 3.5 0- 1.5 - 0- - 3.0 1.5 3.0 2.1 - 2.1 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 2- 2- -67 Min Max 6.7 - - 3.8 - 3.8 0- 1.5 - 0- - 3.0 1.5 3.0 2.3 - 2.3 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 2- 2- -72 Min Max 7.2 - - 4.0 - 4.0 0- 1.5 - 0- - 3.5 1.5 3.5 2.5 - 2.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - 2- 2- -10 Unit Min Max 10 - ns - 4.5 ns - 4.5 ns 0 - ns 1.5 - ns 0 - ns - 4.0 ns 1.5 4.0 ns 3.0 - ns 3.0 - ns 1.5 - ns 1.5 - ns 1.5 - ns 1.5 - ns 1.5 - ns 1.5 - ns 0.5 - ns 0.5 - ns 0.5 - ns 0.5 - ns 0.5 - ns 0.5 - ns 2 - cycle 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. - 11 - December 1999 Rev 1.0 11 Page

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