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PDF K9K1208U0A-YIB0 Data sheet ( Hoja de datos )
| Número de pieza | K9K1208U0A-YIB0 | |
| Descripción | 64M x 8 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K9K1208U0A-YCB0, K9K1208U0A-YIB0
Document Title
64M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
Draft Date Remark
0.0 1. Initial issue
Dec. 6th 2000 Preliminary
- Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection).
So, /SE pin is don’t-cared regardless of external logic input level and is
fixed as low internally.
0.1 1. Changed plane address in Copy-Back Program
Dec. 28th 2000
- A14, the plane address, of source and destination page address must be
the same. => A14 and A25, the plane address, of source and destination
page address must be the same.
0.2 1. In addition, explain WE function in pin description
- The WE must be held high when outputs are activated.
Jan. 17th 2001 Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
1 page  
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
5 Page 
K9K1208U0A-YCB0, K9K1208U0A-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
Buffer
memory
error occurs
Page a
Block A
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
Block B
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet K9K1208U0A-YIB0.PDF ] | |
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