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PDF ICS94222 Data sheet ( Hoja de datos )
| Número de pieza | ICS94222 | |
| Descripción | Programmable System Frequency Generator for PII/III�� | |
| Fabricantes | ETC　 | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS94222
Advance Information
Programmable System Frequency Generator for PII/IIIâ„¢
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
• 3 - CPUs @2.5V, up to 166MHz.
• 17 - SDRAM @ 3.3V, up to 166MHz.
• 7 - PCI @3.3V
• 2 - IOAPIC @ 2.5V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time.
• Programmable PCI_F and PCICLK skew.
• Spread spectrum for EMI control typically by 7dB to 8dB,
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Pin Configuration
AVDD
*FS2/REF1
*PCI_STOP#/REF0
GND
X1
X2
VDD
*MODE/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDD
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDL
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPUCLK_F
51 CPUCLK0
50 VDDL
49 CPUCLK1
48 GND
47 CLK_STOP*
46 SDRAM_F
45 VDDSDR
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDD
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 AVDD48
30 24MHz/FS0*
29 48MHz/FSI*1
Key Specifications:
• CPU – CPU: <175ps
• SDRAM - SDRAM: <500ps
• PCI – PCI: <500ps
• CPU-SDRAM: <500ps
• CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Block Diagram
PLL2
÷2
X1 XTAL
X2 OSC
STOP
FS (3:0)
MODE
CLK_STOP#
PCI_STOP#
SCLK
SDATA
BUFFERIN
PLL1
Spread
Spectrum
LATCH
POR
Control
Logic
Config.
Reg.
STOP
PCI
CLOCK
DIVDER
STOP
STOP
48MHz
24MHz
IOAPIC_F
IOAPIC0
REF [1:0]
2
CPUCLK_F
1
CPUCLK (1:0)
6 PCICLK (5:0)
PCICLK_F
16 SDRAM (15:0)
SDRAM_F
Functionality
FS3 FS2 FS1 FS0
0000
000 1
00 10
00 11
0 100
0 10 1
0 110
0 111
10 0 0
100 1
10 10
10 11
1 10 0
110 1
1 1 10
1111
CPU
(MHz)
80.00
75.00
83.31
66.9
103.00
112.01
68.01
100.7
120.00
114.99
109.99
105.00
140.00
150.00
124.00
133.9
PCICLK
(MHz)
40.00
37.50
41.65
33.45
34.33
37.34
34.01
33.57
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
94222 Rev - 5/10/01
This document is confidential and should not be released
without written consents from ICS.
ADVANCE INFORMATION documents contain information on products in the
formative or design phase development. Characteristic data and other
specifications are design goals. ICS reserves the right to change or discontinue
these products without notice.
1 page  
ICS94222
Advance Information
Brief I2C registers description for ICS94222
Programmable System Frequency Generator
Register N ame
Functionality & Frequency
Select Register
Output Control Registers
Byte
0
1-6
Vendor ID & Revision ID
R eg is ters
7
Byte Count
Read Back Register
8
Watchdog Control Registers 9 Bit [6:0]
VCO Control Selection Bit 9 Bit [7]
D es crip tion
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
PW D Default
See individual
byte description
See individual
byte description
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Writing to this register will configure
byte count and how many byte w ill be
read back. Do not write 00H to this byte.
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
This bit select w hether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
08H
000,0000
0
Watchdog Timer
Count Register
Writing to this register will configure the
10 number of seconds for the watchdog
timer to reset.
10H
VCO Frequency Control
R eg is ters
11-12
These registers control the dividers ratio
into the phase detector and thus control
the V CO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
R eg is ters
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
R eg is ters
15-16
Increment or decrement the group skew
amount as compared to the initial skew .
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to
byte 8.
2. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4. The input is operating at 3.3V logic levels.
5. The data byte format is 8 bit bytes.
6. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
7. At power-on, all registers are set to a default condition, as shown.
This document is confidential and should not be released
without written consent from ICS.
5
5 Page 
ICS94222
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD, VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH VIN = VDD
Input Low Current
IIL1 VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
IIL2 VIN = 0 V; Inputs with pull-up resistors
Operating
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
Supply Current
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
Input frequency
Input Capacitance1
Fi VDD = 3.3 V;
CIN Logic Inputs
Clk Stabilization1
CINX
TSTAB
X1 & X2 pins
From VDD = 3.3 V to 1% target Freq.
1Guaranteed by design, not 100% tested in production.
2
VSS-0.3
-5
-200
12
27
VDD+0.3
0.8
5
V
V
µA
µA
µA
180 mA
16 MHz
5 pF
45 pF
3 ms
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating
Supply Current
ID D 2 .5 O P 6 6
IDD 2 .5 O P 1 0 0
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
72
100
mA
Skew1
tCPU-PCI VT = 1.5 V; VTL = 1.25 V
1.5 4 ns
1Guaranteed by design, not 100% tested in production.
This document is confidential and should not be released
without written consent from ICS.
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS94222.PDF ] | |
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