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PDF SAF7113H Data sheet ( Hoja de datos )
| Número de pieza | SAF7113H | |
| Descripción | 9-bit video input processor | |
| Fabricantes | NXP Semiconductors | |
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SAF7113H
9-bit video input processor
Rev. 03 — 9 May 2005
Product data sheet
1. General description
The 9-bit video input processor is a combination of a two-channel analog preprocessing
circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and
gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder
(PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N and
SECAM), a brightness, contrast and saturation control circuit, a multistandard VBI data
slicer and a 27 MHz VBI data bypass.
The pure 3.3 V CMOS circuit SAF7113H, analog front-end and digital video decoder, is a
highly integrated circuit for desktop video applications. The decoder is based on the
principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and
NTSC signals into ITU-R BT 601 compatible color component values. The SAF7113H
accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is
I2C-bus controlled.
The integrated high performance multistandard data slicer supports several VBI data
standards:
• Teletext 625 lines: WST (World Standard Teletext) and CCST (Chinese teletext)
• Teletext 525 lines: US-WST, NABTS (North-American Broadcast Text System) and
MOJI (Japanese teletext)
• Closed caption: Europe and US (line 21)
• Wide Screen Signalling (WSS)
• Video Programming Signal (VPS)
• Time codes (VITC EBU/SMPTE)
• High-speed VBI data bypass for Intercast application.
2. Features
s Four analog inputs, internal analog source selectors, e.g. 4 × CVBS or 2 × Y/C or
(1 × Y/C and 2 × CVBS)
s Two analog preprocessing channels in differential CMOS style for best
S/N-performance
s Fully programmable static gain or automatic gain control for the selected CVBS or Y/C
channel
s Switchable white peak control
s Two built-in analog anti-aliasing filters
s Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or
Y/C-signals are available on the VPO-port via I2C-bus control
s On-chip clock generator
1 page  
Philips Semiconductors
7. Pinning information
7.1 Pinning
SAF7113H
9-bit video input processor
AI22 1
VSSA1
VDDA1
AI11
2
3
4
AI1D 5
AGND 6
AI12 7
TRST 8
AOUT 9
VDDA0 10
VSSA0 11
SAF7113H
33 VDDDA
32 XTALI
31 XTAL
30 VSSDA
29 VDDDI
28 VSSDI
27 RTS1
26 RTS0
25 RTCO
24 SCL
23 SDA
001aac232
Fig 2. Pin configuration for QFP44
7.2 Pin description
Table 3:
Symbol
AI22
VSSA1
VDDA1
AI11
AI1D
AGND
AI12
TRST
AOUT
VDDA0
VSSA0
Pin description
Pin Type Description
1 I analog input 22
2 P ground for analog supply voltage channel 1
3 P positive supply voltage for analog channel 1 (3.3 V)
4 I analog input 11
5 I differential analog input for AI11 and AI12; has to be connected to
ground via a capacitor; see application diagram of Figure 40
6 P analog signal ground connection
7 I analog input 12
8 I test reset input (active LOW), for boundary scan test; see Table
note 1, Table note 2 and Table note 3
9 O analog test output; for testing the analog input channels; 75 Ω
termination possible
10 P positive supply voltage (3.3 V) for internal Clock Generation Circuit
(CGC)
11 P ground for internal clock generation circuit
9397 750 14231
Product data sheet
Rev. 03 — 9 May 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 75
5 Page 
Philips Semiconductors
SAF7113H
9-bit video input processor
ANALOG INPUT
ADC
NO BLANKING ACTIVE
10
VBLK
<- CLAMP
10
HCL
GAIN ->
10
HSY
10
< CLL
01
< SBOT
10
> WIPE
+ CLAMP
− CLAMP NO CLAMP + GAIN
WIPE = white peak level (254);
SBOT = sync bottom level (1);
CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse;
HCL = horizontal clamp pulse.
Fig 8. Clamp and gain flow
− GAIN fast − GAIN
slow + GAIN
mgc647
8.3 Chrominance processing
The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature
demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0°
and 90° phase relationship to the demodulator axis). The frequency is dependent on the
present color standard. The output signals of the multipliers are low-pass filtered (four
programmable characteristics) to achieve the desired bandwidth for the color difference
signals (PAL and NTSC) or the 0° and 90° FM signals (SECAM).
The color difference signals are fed to the Brightness/Contrast/Saturation block (BCS),
which includes the following five functions:
• Automatic Gain Control (AGC) for chrominance PAL and NTSC
• Chrominance amplitude matching (different gain factors for (R − Y) and (B − Y) to
achieve ITU-R BT 601 levels CR and CB for all standards)
• Chrominance saturation control
• Luminance contrast and brightness
• Limiting YUV to the values 1 (minimum) and 254 (maximum) to fulfil ITU-R BT 601
requirements.
9397 750 14231
Product data sheet
Rev. 03 — 9 May 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 75
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