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PDF SAB9081 Data sheet ( Hoja de datos )
| Número de pieza | SAB9081 | |
| Descripción | Multistandard Picture-In-Picture PIP controller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAB9081
Multistandard Picture-In-Picture
(PIP) controller
Preliminary specification
Supersedes data of 1999 Jan 05
File under Integrated Circuits, IC02
1999 Nov 12
1 page  
Philips Semiconductors
Multistandard Picture-In-Picture (PIP)
controller
Preliminary specification
SAB9081
SYMBOL
n.c.
VSSD(RP)
VSSD(T8) and VSSD(T9)
VDDD(P2)
VSSD(P2)
VSSD(D)
VDDD(D)
FBL
PKOFF
DVSYNC
DCLK
SVSYNC
SCL
SDA
POR
VDDA(SA)
VSSA(SA)
VDDA(SF)
SU
Vref(B)(SA)
SV
Vref(T)(SA)
SY
Vbias(SA)
VSSD(SA)
VDDD(SA)
SHSYNC
T6
VDDA(SP)
VSSA(SP)
VSSA(DP)
VDDA(DP)
T7
DHSYNC
VDDD(MA)
VSSD(MA)
Vbias(MA)
MY
Vref(T)(MA)
MV
PIN
52 to 60
61
62 and 63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TYPE
−
S
S
S
S
S
S
O
O
I
I
I
I/O
I/O
I
S
S
S
I
I/O
I
I/O
I
I/O
S
S
I
I/O
S
S
S
S
I/O
I
S
S
I/O
I
I/O
I
DESCRIPTION
not connected
digital ground for memory periphery
digital ground for test
digital supply voltage for periphery
digital ground for periphery
digital ground for digital core
digital supply voltage for digital core
fast blanking control signal output (CMOS levels; +5 V tolerant)
peak off control signal output (CMOS levels; +5 V tolerant)
vertical sync display channel input (CMOS levels; +5 V tolerant)
test clock input (28 MHz; CMOS levels)
vertical sync for subchannel input (CMOS levels; +5 V tolerant)
input/output serial clock (I2C-bus; CMOS levels; +5 V tolerant)
input/output serial data/acknowledge output (I2C-bus; +5 V tolerant)
power-on reset input (CMOS levels; pull-up resistor connected to VDD)
analog supply voltage for subchannel ADCs
analog ground for subchannel ADCs
analog supply voltage for subchannel front-end buffers and clamps
analog U input for subchannel
input/output analog bottom reference voltage for subchannel ADCs
analog V input for subchannel
input/output analog top reference voltage for subchannel ADCs
analog Y input for subchannel
analog bias reference voltage for subchannel ADCs
digital ground for subchannel ADCs
digital supply voltage for subchannel ADCs
horizontal sync input for subchannel (Vi < VSHSYNC)
test data input/output bit 7 (CMOS levels)
analog supply voltage for subchannel PLL
analog ground for subchannel PLL
analog ground for display channel PLL
analog supply voltage for display channel PLL
test data input/output bit 6 (CMOS levels)
horizontal sync input for display channel (Vi < VDHSYNC)
digital supply voltage for main channel ADCs
digital ground for main channel ADCs
analog bias reference voltage for main channel ADCs
analog Y input for main channel
analog top reference voltage for main channel ADCs
analog V input for main channel
1999 Nov 12
5
5 Page 
Philips Semiconductors
Multistandard Picture-In-Picture (PIP)
controller
Preliminary specification
SAB9081
SDSEL (REPLAY MODE)
Bits SDSel<5:0> select which PIP is read from memory.
Valid numbers are dependent on the maximum value of
SLSel.
DPAL AND SPAL
In normal operation (DPal and SPal are logic 0), the
SAB9081 calculates from the number of incoming lines
whether the signal is NTSC (< 288 lines) or PAL
(≥ 288 lines).
If DPal is set to logic 1, the main window is sized to
276 lines. If DPal is set to logic 1 and the subchannel is still
NTSC, the subchannel picture will be smaller than the
main channel picture (difference of approximately
40 lines).
If SPal is set to logic 1, the subchannel is forced to PAL
mode and 276 lines are acquired instead of 228 in NTSC
mode.
DNTSC AND SNTSC
In normal operation (DNTSC and SNTSC are logic 0), the
SAB9081 calculates from the number of incoming lines
whether the signal is NTSC (< 288 lines) or PAL
(≥ 288 lines).
If DNTSC is set to logic 1, the main window is sized to
228 lines. If DNTSC is set to logic 1 and the subchannel is
still PAL, the subchannel picture will be larger than the
main channel picture (difference of approximately
40 lines).
If SNTSC is set to logic 1, the channel is forced to NTSC
mode and 228 lines are acquired instead of 276 in PAL
mode.
SFBLKPKOFF
Bits SFBlkPkOff<1:0> shift signals FBL and PKOFF with
respect to the YUV output, by half pixels, see Table 4.
Table 4 Shifts of FBL and PKOFF
SFBlkPkOff<1:0>
00
01
10
11
SHIFT OF FBL AND PKOFF
no shift
+0.5 pixel
−0.5 pixel
−1 pixel
I2CHOLD
Bit I2CHold controls the updating of the I2C-bus controlled
function towards the PIP. If set to logic 1, some updates
are on hold until the bit is set to logic 0. At the next main
Vsync, all settings are passed to the PIP functions.
The bits and bytes that are on hold when the I2CHold bit is
set to logic 1 are:
• MPIPON, SPIPON, DNonint and PipMode
• SHBlow and SVBlow
• SHRed and SVRed
• BGHfp and BGVfp
• SDHfp and SDVfp
• SHPic and SVPic
• BGOn, BOn and Prio
• BSel, SBBrt and SBCol
• SDSel
• MDHfp and MDVfp
• HBWidth and VBWidth.
SV1
Bit SV1 controls the internal horizontal offset of the
background. When set to logic 0, the offset is 0.86 µs;
when set to logic 1, the offset is 4.56 µs.
SV2
Bit SV2, when set to logic 0, limits the range of the MAHfp
and SAHfp parameters. Otherwise (bit SV2 set to logic 1),
the parameters have their maximum range (which is
recommended).
SV3
Bit SV3, when set to logic 0, can overrule bit AlgOff when
the main channel is NTSC and the subchannel is PAL. In
this particular case, bit AlgOff is always set to logic 0
internally. Otherwise (bit SV3 set to logic 1), bit AlgOff is
never overruled. It is recommended to set SV3 to logic 1.
1999 Nov 12
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SAB9081.PDF ] | |
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