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PDF SAB9077H Data sheet ( Hoja de datos )

Número de pieza SAB9077H
Descripción Picture-In-Picture PIP controller
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! SAB9077H Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
SAB9077H
Picture-In-Picture (PIP) controller
Preliminary specification
File under Integrated Circuits, IC02
1996 Aug 07

1 page




SAB9077H pdf
Philips Semiconductors
Picture-In-Picture (PIP) controller
Preliminary specification
SAB9077H
PINNING
SYMBOL PIN I/O TYPE
DESCRIPTION
MPVbias
MPHsync
MAVSSD
MAVDDD
MAVbias
MU
1
2
3
4
5
6
I/O E027 analog bias reference for main channel
I HPP01 horizontal synchronization for main channel
I/O E009 digital ground for main channel ADCs and PLLs
I/O E030 digital positive power supply for main channel ADCs and PLLs
I E027 analog bias reference for main channel ADCs
I E027 analog U input for main channel
MAVrefT
MV
7
8
I E027 analog top reference voltage for main channel ADCs
I E027 analog V input for main channel
MAVrefB
9
I E027 analog bottom reference voltage for main channel ADCs
MY 10 I E027 analog Y input for main channel
MAVDDA
MAVSSA
MVSSD
MVDDD
MCVDDD
MCVSSD
MVsync
TDCLK
11
12
13
14
15
16
17
18
I/O E030 analog positive power supply for main channel ADCs
I/O E009 analog ground for main channel ADCs
I/O E009 digital ground for main-channel core
I/O E030 digital positive power supply for main-channel core
I/O E030 digital positive power supply for main-clock buffer
I/O E009 digital ground for main-clock buffer
I HPP01 vertical synchronization for main channel
I HPP01 test clock for display
TC 19 I HPP01 test control
TM0
20 I HPP01 test mode 0
TM1
21 I HPP01 test mode 1
TM2
22 I HPP01 test mode 2
DAI0
23 I HPP04 data bus input from memory; bit 0
DAI7
24 I HPP04 data bus input from memory; bit 7
DAI1
25 I HPP04 data bus input from memory; bit 1
DAI6
26 I HPP04 data bus input from memory; bit 6
DAI2
27 I HPP04 data bus input from memory; bit 2
DAI5
28 I HPP04 data bus input from memory; bit 5
DAI3
29 I HPP04 data bus input from memory; bit 3
DAI4
30 I HPP04 data bus input from memory; bit 4
DT 31 O OPF20 memory data transfer output; active LOW
DAO0 32 O OPF20 data bus output to memory; bit 0
DAO7 33 O OPF20 data bus output to memory; bit 7
DAO1 34 O OPF20 data bus output to memory; bit 1
DAO6 35 O OPF20 data bus output to memory; bit 6
DAO2 36 O OPF20 data bus output to memory; bit 2
DAO5 37 O OPF20 data bus output to memory; bit 5
DAO3 38 O OPF20 data bus output to memory; bit 3
DAO4 39 O OPF20 data bus output to memory; bit 4
SC 40 O OPF20 memory shift clock output
1996 Aug 07
5

5 Page





SAB9077H arduino
Philips Semiconductors
Picture-In-Picture (PIP) controller
Preliminary specification
SAB9077H
Table 3 PIP modes
PIP MODES
NAME
SP
SP
SP
SP
SP
SP
DP
DP
MP3L
MR3R
MR3D
MP7
MP8
MP4
MP9
MP16
MP16
FFS
FFL
MAN
FIGURE
SP small
SP medium
SP large
SP small
SP medium
SP large
DP
twin PIP
POP-left
POP-right
POP-double
POP-double
MP7
Quatro
MP9
MP16
MP16 mix
full field still
full field live
manual
MODE
0000
0000
0000
0000
0000
0000
0000
1001
0010
0010
0010
0011
0011
0001
0100
0101
0110
0000
1000
X111
SUB-CHANNEL MAIN CHANNEL SUB-CHANNEL MAIN CHANNEL
REDH
14
13
12
12
12
14
14
14
14
12
13
14
14
11
X
REDV
14
13
12
12
11
14
14
14
14
12
13
14
14
11
X
REDH
14
13
12
12
12
14
14
12
12
13
14
11
X
REDV
14
13
12
12
11
14
14
12
12
13
14
11
X
HFP
03H
03H
08H
08H
03H
03H
03H
03H
03H
03H
03H
X
VFP
46H
05H
10H
10H
05H
05H
05H
05H
05H
05H
05H
X
HFP
57H
57H
72H
72H
44H
03H
51H
03H
03H
X
VFP
46H
05H
10H
10H
20H
77H
3BH
77H
05H
X
PIP COMBINATIONS
Figures 4, 5 and 6 provide an overview of possible combinations as they can be shown on the screen.
An example of fine positioning is given in the right four columns of Table 3.
More PIP modes can be obtained by varying the horizontal and vertical reduction factors to meet correct aspect ratios
when using 16 : 9 screens.
In manual mode more PIP modes become available. Table 6 with associating text describes how to setup a PIP mode.
1996 Aug 07
11

11 Page







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