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PDF SAB83C166W Data sheet ( Hoja de datos )

Número de pieza SAB83C166W
Descripción High-Performance CMOS 16-Bit Microcontrollers
Fabricantes Infineon Technologies AG 
Logotipo Infineon Technologies AG Logotipo



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C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
SAB 80C166W/
83C166W/
83C166W
SAB 80C166W/83C166W / 83C166W 16-Bit Microcontroller
q High Performance 16-bit CPU with 4-Stage Pipeline
q 100 ns Instruction Cycle Time at 20 MHz CPU Clock
q 500 ns Multiplication (16 × 16 bits), 1 µs Division (32 / 16 bit)
q Enhanced Boolean Bit Manipulation Facilities
q Register-Based Design with Multiple Variable Register Banks
q Single-Cycle Context Switching Support
q Up to 256 KBytes Linear Address Space for Code and Data
q 1 KByte On-Chip RAM
q 32 KBytes On-Chip ROM (SAB 83C166W only)
q Programmable External Bus Characteristics for Different Address Ranges
q 8-Bit or 16-Bit External Data Bus
q Multiplexed or Demultiplexed External Address/Data Buses
q Hold and Hold-Acknowledge Bus Arbitration Support
q 512 Bytes On-Chip Special Function Register Area
q Idle and Power Down Modes
q 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)
q 16-Priority-Level Interrupt System
q 10-Channel 10-bit A/D Converter with 9.7 µs Conversion Time
q 16-Channel Capture/Compare Unit
q Two Multi-Functional General Purpose Timer Units with 5 Timers
q Two Serial Channels (USARTs)
q Programmable Watchdog Timer
q Up to 76 General Purpose I/O Lines
q Direct clock input without prescaler
q Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards
q On-Chip Bootstrap Loader
q 100-Pin Plastic MQFP Package (EIAJ)
Semiconductor Group
1
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SAB83C166W pdf
SAB 80C166W/83C166W
Pin Definitions and Functions (cont’d)
Pin Symbol
No.
29 NMI
29 ALE
26 RD
30 - 37 P1.0 –
40 - 47 P1.15
48 - 53 P5.0 –
56 - 59 P5.9
62 - 77 P2.0 –
P2.15
62
75
76
77
Input (I) Function
Output (O)
I Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI pin
must be low in order to force the SAB 80C166W/83C166W to
go into power down mode. If NMI is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pull NMI high externally.
O Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
O External Memory Read Strobe. RD is activated for every
external instruction or data read access.
I/O Port 1 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode..
I Port 5 is a 10-bit input-only port with Schmitt-Trigger
I characteristics. The pins of Port 5 also serve as the (up to 10)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x).
I/O Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The following Port 2 pins also serve for alternate functions:
I/O
P2.0
CC0IO CAPCOM: CC0 Cap.-In/Comp.Out
... ... ...
I/O P2.13 CC13IO CAPCOM: CC13 Cap.-In/Comp.Out,
O BREQ External Bus Request Output
I/O P2.14 CC14IO CAPCOM: CC14 Cap.-In/Comp.Out,
O HLDA External Bus Hold Acknowl. Output
I/O P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,
I HOLD External Bus Hold Request Input
Semiconductor Group
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SAB83C166W arduino
SAB 80C166W/83C166W
A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value
upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient SAB 80C166W/83C166W instruction set which includes the
following instruction classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
Semiconductor Group
11

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