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PDF SAB83C166-5M-T3 Data sheet ( Hoja de datos )

Número de pieza SAB83C166-5M-T3
Descripción 16-Bit CMOS Single-Chip Microcontroller
Fabricantes Infineon Technologies AG 
Logotipo Infineon Technologies AG Logotipo



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No Preview Available ! SAB83C166-5M-T3 Hoja de datos, Descripción, Manual

Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller
SAB 80C166/83C166
Data Sheet 09.94

1 page




SAB83C166-5M-T3 pdf
SAB 80C166/83C166
Pin Definitions and Functions
Symbol
P4.0 –
P4.1
Pin Input
Number Output
16-17 I/O
XTAL1
XTAL2
16
17
20
19
O
O
I
O
BUSACT, 22
EBC1, 23
EBC0
24
I
I
I
RSTIN 27
I
RSTOUT 28
O
Function
Port 4 is a 2-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance
state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0
A16 Least Significant Segment Addr. Line
P4.1
A17 Most Significant Segment Addr. Line
XTAL1: Input to the oscillator amplifier and input to the
internal clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while
leaving XTAL2 unconnected. Minimum and maximum high/low
and rise/fall times specified in the AC Characteristics must be
observed.
External Bus Configuration selection inputs. These pins are
sampled during reset and select either the single chip mode or
one of the four external bus configurations:
BUSACT EBC1 EBC0 Mode/Bus Configuration
0 0 0 8-bit demultiplexed bus
0 0 1 8-bit multiplexed bus
0 1 0 16-bit multiplexed bus
0 1 1 16-bit demultiplexed bus
1 0 0 Single chip mode
1 0 1 Reserved.
1 1 0 Reserved.
1 1 1 Reserved.
ROMless versions must have pin BUSACT tied to ‘0’.
Reset Input with Schmitt-Trigger characteristics. A low level at
this pin for a specified duration while the oscillator is running
resets the SAB 80C166. An internal pullup resistor permits
power-on reset using only a capacitor connected to VSS.
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
Semiconductor Group
4

5 Page





SAB83C166-5M-T3 arduino
SAB 80C166/83C166
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the SAB 80C166’s instructions can be executed in just
one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
32 KByte in the
SAB 83C166
Figure 4
CPU Block Diagram
Semiconductor Group
10
1 KByte

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