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PDF SAB-C165-L25M Data sheet ( Hoja de datos )

Número de pieza SAB-C165-L25M
Descripción 16-Bit Single-Chip Microcontroller
Fabricantes Infineon Technologies AG 
Logotipo Infineon Technologies AG Logotipo



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No Preview Available ! SAB-C165-L25M Hoja de datos, Descripción, Manual

Data Sheet, V2.0, Dec. 2000
C165
16-Bit Single-Chip Microcontroller
Microcontrollers
Never stop thinking.

1 page




SAB-C165-L25M pdf
16-Bit Single-Chip Microcontroller
C166 Family
C165
C165
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
• On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer
• Up to 77 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Power Supply: the C165 can operate from a 5 V or a 3 V power supply
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 100-Pin MQFP Package (0.65 mm pitch)
• 100-Pin TQFP Package (0.5 mm pitch)
Data Sheet
1 V2.0, 2000-12

5 Page





SAB-C165-L25M arduino
C165
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr Pin Nr Input Function
TQFP MQFP Outp.
P4 IO Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 4 can be used to
output the segment address lines:
P4.0 23 25
O
A16 Least Significant Segment Address Line
P4.1 24 26
O
A17 Segment Address Line
P4.2 25 27
O
A18 Segment Address Line
P4.3 26 28
O
A19 Segment Address Line
P4.4 29 31
O
A20 Segment Address Line
P4.5 30 32
O
A21 Segment Address Line
P4.6 31 33
O
A22 Segment Address Line
P4.7 32 34
O
A23 Most Significant Segment Address Line
RD 33 35 O
External Memory Read Strobe. RD is activated for
every external instruction or data read access.
WR/ 34
WRL
36
O
External Memory Write Strobe. In WR-mode this pin
is activated for every external data write access. In
WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data
write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
READY 35 37
I
Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory
access will force the insertion of memory cycle
waitstates until the pin returns to a low level.
An internal pullup device holds this pin high when
nothing is driving it.
ALE 36 38
O
Address Latch Enable Output. Can be used for
latching the address into external memory or an
address latch in the multiplexed bus modes.
EA 37 39 I
External Access Enable pin. A low level at this pin
during and after Reset forces the C165 to begin
instruction execution out of external memory. A high
level forces execution out of the internal program
memory.
“ROMless” versions must have this pin tied to ‘0’.
Data Sheet
7 V2.0, 2000-12

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