PDF SAA8122AEL Data sheet ( Hoja de datos )

Número de pieza	SAA8122AEL
Descripción	Digital Still Camera Processor ImagIC family
Fabricantes	NXP Semiconductors
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No Preview Available ! SAA8122A Digital Still Camera Processor (ImagIC family) Rev. 01 — 20 April 2000 Objective speciﬁcation 1. Description The DSC SAA8122A is a high performance, low power, single-chip Million Instructions Per Second (MIPS) based signal processor, part of the ImagIC family, which is dedicated to image processing, compression, formatting and storage. The DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022, 2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy implementation of a complete system solution and fast development of high performance consumer digital still cameras. The SAA8122A is designed as a single-chip device, able to perform all treatments and connections required for a wide range of Digital Still Cameras. Its embedded RISC CPU, for which the development environment is available, enables shorter development and validation cycles, as well as faster feature upgrade. Since one of the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a DSP (with advanced embedded algorithm) for camera signal processing is integrated with a high level of programmability for pulses generation. The JPEG core is hardware based in order to allow high-speed image data compression. c 2. Featuresc 2.1 General s Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA), with RGB Bayer ﬁlters up to 2 Mpixels s Performs an advanced RGB to YUV conversion s Includes a smart measurement unit to speed up the control loop (focus, auto white balance, etc.) s Supports a wide range of LCD and TV formats (both NTSC and PAL) with text insertion features s Includes an embedded JPEG encoder/decoder unit s Includes a MIPS PR3001 CPU, running at a frequency in a range from 12 to 28 MHz s PRISC compatible PI-bus architecture, interrupt, power management, clock and reset architectures s Includes a dedicated video bus supporting SDRAM memory for picture storage 1 page Philips Semiconductors SAA8122A Digital Still Camera Processor (ImagIC family) handbook, full pagewidth lens CCD FXA1022 to LCD to TV TDA9952 10 SAA8122A to cards (SSFDC, CF) V-DRIVER TDA9991 Fig 2. System block diagram. 6. Pinning information 6.1 Pinning USB IRDA to PC FCE687 handbook, halfpage V U T R P N M L K J H G F E D C B A 2 4 6 8 10 12 14 16 18 1 3 5 7 9 11 13 15 17 SAA8122AEL FCE677 Fig 3. Pin conﬁguration (bottom view). 6.2 Pin description Table 3: Pin description Symbol Pin VDDD VSSA(DLL) VDDA(DLL) DISP_VSYNC A1 A2 A3 A4 IO1/IRQ17 A5 VDDA(LCDG) VDDA(OUTPUT2) A6 A7 Type - - - O I/O P P Description digital supply voltage analog ground for DLL of PPG analog supply voltage for DLL of PPG digital vertical synchronization signal I/O port 0 bit 1 or interrupt request 17 analog supply voltage for DAC component G analog supply voltage for DAC video output 2 9397 750 07048 Objective speciﬁcation Rev. 01 — 20 April 2000 © Philips Electronics N.V. 2000. All rights reserved. 5 of 26 5 Page Philips Semiconductors SAA8122A Digital Still Camera Processor (ImagIC family) Table 3: Pin description…continued Symbol Pin Type SC_CLE M18 O SD_A[12] N1 O SD_A[13] N2 O SD_A[14] N3 O SD_A[10] N4 O SD_A[6] N5 O SD_A[5] N6 O VDD VDD VDD VDD VDD SC_ALE N7 - N8 - N9 - N10 - N11 - N12 O PC2_CE1 N13 O PC2_CE2 N14 O PC_REG N15 O PC_WAIT1 N16 O IOWR_WE N17 O IORD_RE N18 O SD_CLKOUT P1 O SD_CLKIN P2 I SD_CS2 P3 O SD_CLKEN P4 O SD_A[11] P5 O VDD SD_D[7] P6 P7 - I/O IO25 P8 I/O IO38 P9 I/O A25 P10 I/O A21 P11 I/O VDD P12 - A14 P13 I/O SCLK P14 O A9 P15 I/O CAS0 P16 O PC1_CE1 PC1_CE2 SD_CS0 SD_CS1 SD_CS3 P17 P18 R1 R2 R3 O O O O O 9397 750 07048 Objective speciﬁcation Description EBIU controller CLE signal for SSFDC card SDRAM controller address bus bit 12 SDRAM controller address bus bit 13 SDRAM controller address bus bit 14 SDRAM controller address bus bit 10 SDRAM controller address bus bit 6 SDRAM controller address bus bit 5 supply voltage supply voltage supply voltage supply voltage supply voltage EBIU controller ALE signal for SSFDC card EBIU controller CE1 signal for PC card 2; active LOW EBIU controller CE2 signal for PC card 2; active LOW EBIU controller REG signal for PC cards; active LOW EBIU controller WAIT signal for PC card 1; active LOW EBIU controller IORD signal for PC cards; active LOW EBIU controller IORD signal for PC cards; active LOW SDRAM controller clock output SDRAM controller clock input SDRAM controller chip select for memory 2; active LOW SDRAM controller clock enable SDRAM controller address bus bit 11 supply voltage SDRAM controller data bus bit 7 I/O port 3 bit 1 I/O port 4 bit 6 EBIU A25 (Strapin[0] during boot sequence) EBIU A21 (Strapin[4] during boot sequence) supply voltage EBIU A14 EBIU controller clock signal for external peripherals EBIU A9 EBIU controller CAS signal for DRAM memory for lower byte; used as data strobe signal for lower byte for general chip select; active LOW EBIU controller CE1 signal for PC card 1; active LOW EBIU controller CE2 signal for PC card 1; active LOW SDRAM controller chip select for memory 0; active LOW SDRAM controller chip select for memory 1; active LOW SDRAM controller chip select for memory 3; active LOW Rev. 01 — 20 April 2000 © Philips Electronics N.V. 2000. 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