PDF SAA7826HL Data sheet ( Hoja de datos )

Número de pieza	SAA7826HL
Descripción	CD audio decoder/ digital servo and filterless DAC with integrated pre-amp and laser control
Fabricantes	NXP Semiconductors
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INTEGRATED CIRCUITS DATA SHEET SAA7826 CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control Product speciﬁcationSupersedes data of 2003 Aug 04 2003 Oct 01 1 page Philips Semiconductors CD audio decoder, digital servo and ﬁlterless DAC with integrated pre-amp and laser control Product speciﬁcation SAA7826 5 BLOCK DIAGRAM handbook, full pagewidth VSSA2 VSSA1 VSSA3 SENSE D1 D2 D3 D4 R1 R2 MONITOR EXFILTER LFPOWER 9 10 11 12 13 14 5 17 20 3 4 2 1 VDDA1 VDDA2 IREF VREFO SCL SDA RAB SILD TEST1 TEST2 TEST3 TEST4 OSCIN OSCOUT CLK16 CLK4/12 CDTRDY CDTDATA CDTCLK SFSY SUB RCK SBSY STATUS RESET DC OFFSET COMPENSATION 7 16 MONITOR ADC LASER POWER CONTROL LOGIC LASER 80 LASER VOLTAGE BUFFER HF AND LF CAPTURE ANTI ALIAS 6 8 BIAS GENERATOR CONTROL PART D1 TO D4 SUM DISC ADC HIGH-PASS FILTER CONTROL FUNCTION OUTPUT STAGES 64 RA 65 FO 66 SL 53 52 54 MICROCONTROLLER INTERFACE 55 DATA SLICER AND THRESHOLD CONTROL MOTOR CONTROL 15 CSLICE 67 MOTO1 68 MOTO2 76 77 78 TEST 79 DIGITAL PLL ERROR CORRECTOR FLAGS 39 CFLAG 19 18 49 TIMING 50 EFM DEMODULATOR AUDIO PROCESSOR SRAM 36 EBU INTERFACE 62 DOBM 37 CD TEXT 38 INTERFACE 59 RAM ADDRESSER SERIAL DATA INTERFACE 45 48 47 46 EF SCLK WCLK DATA 58 INTERFACE CONTROL 57 60 SUBCODE PROCESSOR PEAK SERIAL 44 SCLI DATA (LOOPBACK) INTERFACE 43 42 WCLI SDI DECODER 56 MICRO- SAA7826 DETECT DEM DAC 27 22 23 26 25 24 21 DACVpos DACRP DACRN DACLP DACLN DACVref DACGND CONTROLLER INTERFACE VERSATILE PINS INTERFACE 51 40 61 69 41 63 70 71 72 73 74 75 KILL 34 35 HEADPHONE BUFFERS 33 28 29 32 30 31 BUFINR BUFINL BUFOUTR BUFOUTL MBL742 VSSD1 VSSD3 VDDD2 VSSD2 VDDD1 VDDD3 V1 V2 V3 V4 V5 LKILL RKILL BUFVpos BUFGND Fig.1 Block diagram. 2003 Oct 01 5 5 Page Philips Semiconductors CD audio decoder, digital servo and ﬁlterless DAC with integrated pre-amp and laser control Product speciﬁcation SAA7826 7.4 Data slicer and bit clock regenerator The SAA7826 has an integrated adaptive data slicer which is clocked at 67 MHz. The slice level is controlled by internal current sources which are switched onto and integrated by the external capacitor connected to the CSLICE pin. The currents are switched under the control of a Digital Phase-Locked loop (DPLL). Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required. The bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization. The PLL loop response is illustrated in Fig.5. For certain applications an off-track input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but can be input via pin V1 if selected by register C. If this flag is HIGH, the SAA7826 assumes that its servo part is following the wrong track, and will flag all incoming HF data as incorrect. handbook, halfpage PLL loop response 3. PLL, LPF 2. PLL bandwidth 1. PLL integrator f MGS178 Points 1, 2 and 3 are all programmable via decoder register 8. Fig.5 Digital PLL loop response. 7.5 DC offset cancellation Unwanted DC offsets can exist within the photo-diode signals and are defined as the DC present in the system when the laser diode is switched off. They arise from various sources of imperfection within the system such as leakage in the photo diodes and offsets in the Optical Pick-Up (OPU) circuitry. The SAA7826 is capable of measuring these offsets and minimizing them. 7.5.1 OFFSET CANCELLATION A number of registers are associated with the DC offset cancellation function; these registers are given in Table 3. The measurement time of the DC offset is regulated by new shadow register C (bank 2). A longer time will yield more accurate results but will result in greater measurement durations. New shadow register 3 (bank 3) is used to select which diode is to be measured. 7.5.2 READING BACK THE DC OFFSET VALUE The microcontroller reads the DC offset measurements in order to calculate the correct cancellation value [for writing back to new shadow register 7 (bank 3)]. This is achieved by using the STATUS pin and setting decoder register 7 to XX10. Shadow register C (bank 3) can then be used to control the STATUS pin output; the register settings are given in Table 20. Once the measurement time has been set and the diode selected, the STATUS pin should be set to read the DC offset ready flag [new shadow register C (bank 3) = X01X]. This signal toggles HIGH after the prescribed measurement time. Changing the diode selection results in the measurement timer being automatically reset. The microcontroller can read back the measurement by setting the STATUS pin to output the DC offset value [new shadow register C (bank 3) = X10X]. The offset value is repeatedly streamed out through the STATUS pin and is UART compatible. It should be noted that the MSB is inverted and will require re-inverting after the offset value has been captured. Timing information for this signal is illustrated in Fig.6. The final DC cancellation value (as calculated by the microcontroller) can then be written to new shadow register 7 (bank 3). This is a multiple write register containing the cancellation values for all six diodes. 2003 Oct 01 11 11 Page

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